MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 139
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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5.5.3.2
The command sequence diagram in
represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system
sends to the debug module; the bottom half indicates the debug module’s response to the previous
development system commands. Command and result transactions overlap to minimize latency.
The sequence is as follows:
Freescale Semiconductor
•
•
In cycle 1, the development system command is issued (
responds with either the low-order results of the previous command or a command complete status
of the previous command, if no results are required.
In cycle 2, the development system supplies the high-order 16 address bits. The debug module
returns a not-ready response unless the received command is decoded as unimplemented, which is
indicated by the illegal command encoding. If this occurs, the development system should
retransmit the command.
COMMANDS TRANSMITTED TO THE DEBUG MODULE
RESPONSES FROM THE DEBUG MODULE
READ (LONG)
???
Command Sequence Diagrams
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
RESULTS FROM PREVIOUS COMMAND
COMMAND CODE TRANSMITTED DURING THIS CYCLE
MCF5272 ColdFire
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY DEBUG MODULE
"NOT READY"
MS ADDR
"ILLEGAL"
XXX
Figure 5-16. Command Sequence Diagram
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
Figure 5-16
®
Integrated Microprocessor User’s Manual, Rev. 3
DATA UNUSED FROM
THIS TRANSFER
"NOT READY"
"NOT READY"
NEXT CMD
LS ADDR
LOW-ORDER 16 BITS OF MEMORY ADDRESS
shows serial bus traffic for commands. Each bubble
NOTE
LOCATION
MEMORY
READ
NONSERIAL-RELATED ACTIVITY
READ
HIGH- AND LOW-ORDER
16 BITS OF RESULT
in this example). The debug module
ERROR OCCURS ON
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
SEQUENCE TAKEN IF BUS
MEMORY ACCESS
"NOT READY"
MS RESULT
XXX
XXX
XXXXX
BERR
XXX
"NOT READY"
COMMAND
NEXT CMD
LS RESULT
NEXT CMD
NEXT
CODE
Debug Support
5-21
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