MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 538

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Index
Stack pointer, 2-5,
Status register,
STOP instruction, 5-4,
Suggested reading,
Supervisor
System configuration and protection,
System protection register,
T
TAP controller,
TCN0–TCN3,
Test access port,
Timer module
Timers
Timing
Timings
Transmit signal timing,
Index-8
base address register,
initialization,
overview and operation,
programming model,
programming model,
capture registers,
counters,
event registers,
general-purpose registers,
mode registers,
operation,
overview, 1-7,
reference registers,
bus software watchdog,
branch instruction execution,
clock input and output,
fast Ethernet AC,
GPIO port AC,
JTAG AC,
MAC unit instructions,
MII
MII async input signal,
MOVE instructions,
one operand,
PLI,
processor bus input,
SDRAM interface,
serial management channel,
timer module AC,
two operands,
USART AC,
USB interface AC,
SDRAM refresh,
transmit signal,
23-23
15-4
15-1
23-30
15-4
2-8
2-22
23-22
4-4
21-3
2-22
1-7
15-1
15-5
15-3
23-28
2-5
1-xliii
15-4
9-20
23-17
23-18
23-21
23-14
15-4
23-29
23-6
2-20
5-16
4-2
2-7
23-18
4-3
23-5
3-4
23-19
MCF5272 ColdFire
20-24
4-2
6-6
15-3
23-20
2-25
1-5
®
Integrated Microprocessor User’s Manual, Rev. 3
U
UART modules
USB
bus operation
clock source baud rates,
external clock,
FIFO stack in UART0,
initialization sequence,
looping modes,
mode registers,
multidrop mode,
overview,
programming,
receiver enabled,
register description,
serial overview,
signal definitions,
transmitter/receiver
transmitting in UART mode,
access times,
alternate settings register,
architecture,
attachment detection,
buffer descriptors,
class- and vendor-specific request operation,
clock generator,
configuration and interface changes,
configuration RAM, 12-28,
control logic,
control, bulk, and interrupt endpoints,
data flow,
device configuration example,
endpoint
endpoint control registers, 12-17,
FIFO configuration,
frame number match register,
function address register,
IN endpoints, 12-33,
initialization,
interrupt acknowledge cycles,
read cycles,
write cycles,
automatic echo,
local loop-back,
remote loop-back,
clock source,
modes,
controllers,
data present registers,
data registers,
FIFOs,
halt feature,
interrupt mask registers,
status interrupt registers,
12-30
16-22
1-6
12-32
12-2
12-30
12-4
12-31
12-5
16-29
16-30
12-35
16-21
16-29
16-4
16-26
16-19
16-2
12-4
12-27
16-28
16-24
16-18
16-27
16-27
11-34
16-2
12-32
16-27
12-34
12-36
16-25
16-30
16-20
12-28
12-11
12-12
12-26
12-25
12-30
16-22
12-9
12-29
16-29
Freescale Semiconductor
12-20
12-31
12-33
12-34