MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 468

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Bus Operation
Figure 20-20
Clock 1 (C1)
Clock 2 (C2)
Clock 3 (C3)
20-20
SDCLK
A[22:0]
D[31:0]
OE
R/W
CSn
BS[3:0]
TEA
The write cycle starts in C1. During C1, the MCF5272 places valid values on the address bus
(A[22:0]) and the chip select signal.
During C2, the MCF5272 drives the data bus, the byte strobes, and R/W.
During C3, the selected device detects an error and asserts TEA. At the end of C3 or Cx, the
MCF5272 samples the level of TEA. If it is asserted, the transfer of the longword is aborted and
the transfer terminates.
Figure 20-20. Longword Write Access To 32-Bit Port Terminated with TEA Timing
(H)
shows a longword write access to a 32-bit port with a transfer error.
This example shows TEA being asserted during C3. TEA can be asserted
earlier or later than C3.
If TA is asserted when debug transfer error-acknowledge (TEA) is asserted,
the transfer is terminated with a bus error.
MCF5272 ColdFire
C1
®
C2
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
NOTE
C3
Cx
Freescale Semiconductor
C4