MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 107

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

ROMBAR can be configured similarly, as described in
Power
4.4
The ROM modules has the following features:
4.4.1
The ROM module contains tabular data that the ColdFire core can access in a single cycle. The ROM can
be located on any 16-Kbyte address boundary in the 4-Gbyte address space.
Between Local Memory
resources.
4.4.2
The MCF5272 implements the ROM base address register (ROMBAR), shown in
described in the following section.
4.4.2.1
ROMBAR determines the base address location of the internal ROM module, as well as the definition of
the allowable access types. ROMBAR can be accessed in supervisor mode using the MOVEC instruction
with an Rc value of 0xC00. It can also be read when the processor is in background debug mode (BDM).
To access the ROM module, ROMBAR should be initialized with the appropriate base address.
ROMBAR fields are described in
Freescale Semiconductor
•
•
•
•
•
•
•
Address
Reset
Management.”
Field
16-Kbyte ROM, organized as 4K x 32 bits
Contains data tables for soft HDLC (high-level data link control)
The ROM contents are not customizeable
Single-cycle access
Physically located on ColdFire core's high-speed local bus
Byte, word, longword address capabilities
Programmable memory mapping
R/W
ROM Overview
ROM Operation
ROM Programming Model
31
ROM Base Address Register (ROMBAR)
MCF5272 ColdFire
Modules,” describes priorities when a fetch address hits multiple local memory
Figure 4-2. ROM Base Address Register (ROMBAR)
BA
Table
®
Integrated Microprocessor User’s Manual, Rev. 3
—
4-4.
W for CPU; R/W for debug
CPU space + 0xC00
14
13
Section 4.4.2.2, “Programming ROMBAR for
—
8
7
—
00
6
Section 4.1, “Interactions
C/I SC SD UC UD
—
5
Figure 4-2
—
4
—
3
—
2
and
Local Memory
—
1
V
0
0
4-5