MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 75

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

2.2.1.6
Figure 2-3
described as follows:
2.2.2
The MCF5272 supervisor programming model is shown in
the supervisor programming model to implement operating system functions and provide memory and I/O
control. The supervisor programming model provides access to the user registers and additional supervisor
registers, which include the upper byte of the status register (SR), the vector base register (VBR), and
registers for configuring attributes of the address space connected to the Version 2 processor core. Most
supervisor-mode registers are accessed by using the MOVEC instruction with the control register
definitions in
Freescale Semiconductor
•
•
•
Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the
results of MAC operations.
Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask
for MAC instructions that fetch operands from memory. It is useful in the implementation of
circular queues in operand memory.
MAC status register (MACSR)—This 8-bit register defines configuration of the MAC unit and
contains indicator flags affected by MAC instructions. Unless noted otherwise, MACSR indicator
flag settings are based on the final result, that is, the result of the final operation involving the
product and accumulator.
shows the registers in the MAC portion of the user programming model. These registers are
Supervisor Programming Model
MAC Programming Model
Table
2-2.
MCF5272 ColdFire
Rc[11–0]
0xC00
0xC04
0xC0F
0x002
0x004
0x005
0x801
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Vector base register (VBR)
ROM base address register
RAM base address register (RAMBAR)
Module base address register (MBAR)
Table 2-2. MOVEC Register Map
®
Integrated Microprocessor User’s Manual, Rev. 3
Register Definition
Figure
2-3. Typically, system programmers use
ColdFire Core
2-7