MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 531

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Index
A
Access control register,
ACR0 and ACR1,
Activate low-power register,
Address bus,
Address variant,
Addressing
Addressing mode summary,
Arbitration, bus,
Architecture overview,
Async inputs signal timing,
Audience,
B
Baud rate
Branch instruction execution
Buffer descriptors
Buffering and impedance matching,
Bus
Byte strobes,
Freescale Semiconductor
mode summary,
calculating,
selection,
timing,
Ethernet,
USB controller,
arbitration,
burst data transfers,
configurations overview,
data transfer mechanism,
errors,
exceptions,
external interface,
external interface types,
interface for FLASH/SRAM,
interrupt acknowledge cycles,
master reset,
misaligned operands,
normal reset,
read/write (R/W),
reset operation,
sizing,
soft reset operation,
software watchdog timer reset operation,
transfer acknowledge (TA),
transfer error acknowledge (TEA),
20-19
20-4
2-25
1-xl
11-34
14-6
20-2
20-8
20-21
20-3
16-20
20-22
20-23
5-4
20-21
20-21
11-34
4-14
2-12
20-2
1-5
20-17
20-25
1-4
20-18
4-14
MCF5272 ColdFire
20-7
1-7
20-4
23-19
2-12
6-10
20-2
20-8
20-19
B-1
20-3
20-24
®
Integrated Microprocessor User’s Manual, Rev. 3
C
Cache
Cache control register,
Caches
CAM interface,
CCR,
Chip select
Chip selects
Clock generator, USB,
ColdFire
ColdFire core
Condition code register,
Conventions
Core
D
Data
Debug
configuration register,
registers, access control,
coherency and validation,
miss fetch algorithm/line fills,
base registers,
CS0 special case,
option registers,
overview, features, usage,
registers,
general overview,
documentation,
addressing mode summary,
condition code register (CCR),
exception processing overview,
features and enhancements,
instruction set summary,
integer data formats,
programming model,
status register,
supervisor programming model,
user programming mode,
notational,
terminology,
version 2
bus,
attribute trigger register,
BDM command set summary,
overview,
2-6
20-2
8-2
1-xliv
1-4
1-xlvii
11-6
8-3
2-8
1-xliii
8-5
8-2
1-5
4-12
12-4
2-9
2-4
2-6
2-9
2-9
5-7
2-13
2-4
4-8
8-1
2-12
2-1
4-10
5-19
2-6
2-25
2-7
Index-1