MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 70

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

ColdFire Core
2.1.1.1
The IFP generates instruction addresses and fetches. Because the fetch and execution pipelines are
decoupled by a three longword FIFO buffer, the IFP can prefetch instructions before the OEP needs them,
minimizing stalls.
2.1.1.2
The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register file feeding an
arithmetic/logic unit (ALU). For simple register-to-register instructions, the first stage of the OEP
performs the instruction decode and fetching of the required register operands (OC), while the actual
instruction execution is performed in the second stage (EX).
For memory-to-register instructions, the instruction is effectively staged through the OEP twice in the
following way:
2-2
•
•
•
•
The instruction is decoded and the components of the operand address are selected (DS).
The operand address is generated using the execute engine (AG).
The memory operand is fetched while any register operand is simultaneously fetched (OC).
The instruction is executed (EX).
Instruction Fetch Pipeline (IFP)
Operand Execution Pipeline (OEP)
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
MCF5272 ColdFire
DSOC
AGEX
IAG
IC
IB
Decode & Select,
Instruction Buffer
Operand Fetch
Generation,
Fetch Cycle
Instruction
Generation
Instruction
®
Figure 2-1. ColdFire Pipeline
Address
Address
Execute
Integrated Microprocessor User’s Manual, Rev. 3
FIFO
Address [31:0]
Data[31:0]
Freescale Semiconductor