MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 14

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Paragraph
Number
2.3 Integer Data Formats ..................................................................................................................... 2-9
2.4 Organization of Data in Registers ................................................................................................ 2-10
2.5 Addressing Mode Summary ........................................................................................................ 2-12
2.6 Instruction Set Summary ............................................................................................................. 2-13
2.7 Instruction Timing ........................................................................................................................ 2-19
2.8 Exception Processing Overview .................................................................................................. 2-25
3.1 Overview ........................................................................................................................................ 3-1
3.2 MAC Instruction Execution Timings ............................................................................................. 3-4
xiv
2.2.2 Supervisor Programming Model ........................................................................................ 2-7
2.4.1 Organization of Integer Data Formats in Registers .......................................................... 2-10
2.4.2 Organization of Integer Data Formats in Memory ........................................................... 2-11
2.6.1 Instruction Set Summary .................................................................................................. 2-15
2.7.1 MOVE Instruction Execution Times ................................................................................ 2-20
2.7.2 Execution Timings—One-Operand Instructions .............................................................. 2-22
2.7.3 Execution Timings—Two-Operand Instructions .............................................................. 2-22
2.7.4 Miscellaneous Instruction Execution Times ..................................................................... 2-24
2.7.5 Branch Instruction Execution Times ................................................................................ 2-25
2.8.1 Exception Stack Frame Definition ................................................................................... 2-27
2.8.2 Processor Exceptions ........................................................................................................ 2-28
3.1.1 MAC Programming Model ................................................................................................. 3-2
3.1.2 General Operation .............................................................................................................. 3-3
3.1.3 MAC Instruction Set Summary .......................................................................................... 3-4
3.1.4 Data Representation ............................................................................................................ 3-4
2.2.1.2 Address Registers (A0–A6) .................................................................................. 2-5
2.2.1.3 Stack Pointer (A7, SP) .......................................................................................... 2-5
2.2.1.4 Program Counter (PC) .......................................................................................... 2-6
2.2.1.5 Condition Code Register (CCR) ........................................................................... 2-6
2.2.1.6 MAC Programming Model ................................................................................... 2-7
2.2.2.1 Status Register (SR) .............................................................................................. 2-8
2.2.2.2 Vector Base Register (VBR) ................................................................................. 2-8
2.2.2.3 Cache Control Register (CACR) .......................................................................... 2-9
2.2.2.4 Access Control Registers (ACR0–ACR1) ............................................................ 2-9
2.2.2.5 ROM Base Address Register (ROMBAR) ........................................................... 2-9
2.2.2.6 RAM Base Address Register (RAMBAR) ........................................................... 2-9
2.2.2.7 Module Base Address Register (MBAR) ............................................................. 2-9
MCF5272 ColdFire
Hardware Multiply/Accumulate (MAC) Unit
Table of Contents (Continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Chapter 3
Title
Freescale Semiconductor
Number
Page