MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 214

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

DMA Controller
10.2
The DMA address mode determines how the address output by the channel is updated after a transfer to
be ready for the next transfer. The two following modes are supported:
10.3
The MCF5272 DMA controller supports a single DMA channel which can be used for
memory-to-memory transfers.
10.3.1
The DMR controls various operation modes, principally the request and addressing modes. Fields include
the transfer size and modifier, transfer direction, channel enable and reset.
Table 10-2
10-2
29–20
Bits
31
30
•
•
Reset
Reset
Field RESET
Field
Addr
R/W
R/W
Static address mode—The address remains unchanged after the transfer completes. This mode
should be used when the source or destination address is the FIFO data port of an on-chip
peripheral.
Increment address mode—In increment address mode, the address is incremented at the end of the
transfer by the number of bytes transferred. This mode should be used when a source or destination
address is in external memory.
RESET Reset. Writing a 1 to this location causes the DMA controller to reset to a condition where no transfers are
Name
DMA Address Modes
DMA Controller Registers
EN
—
describes DMR fields.
DMA Mode Register (DMR)
—
31
15
0
taking place. EN is cleared, preventing new transfers.
Enable. Controls whether the DMA channel is enabled to perform transfers.
0 DMA transfers are disabled.
1 DMA transfers are enabled. The DMA controller can respond to requests from the peripheral or generates
Reserved, should be cleared.
internal requests in dual address mode, so long as the conditions described under the DMA interrupt
flags (see
EN
30
14
DSTM
MCF5272 ColdFire
01
29
13
Section 10.3.2, “DMA Interrupt Register
12
DSTT
Figure 10-1. DMA Mode Register (DMR)
1_00
Table 10-2. DMR Field Descriptions
®
10
Integrated Microprocessor User’s Manual, Rev. 3
9
DSTS
0000_0000_0000_0000
01
MBAR + 0x00E0
8
—
R/W
R/W
Description
—
0
7
(DIR)”) do not prevent transfers from going ahead.
—
0
6
SRCM
1
5
20
4
SRCT
1_01
19
RQM
Freescale Semiconductor
18
2
17
1
SRCS
—
01
16
0