MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 152

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Debug Support
5.6.1
Breakpoint hardware can be configured to respond to triggers in several ways. The response desired is
programmed into TDR. As shown in
(CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status,
operands, or branch addresses.
The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR read when either
a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled.
Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates,
a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before
the excepting instruction is executed. All other breakpoint events are recognized on the processor’s local
bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these
interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] = 01, a
breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher
than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the
processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC
breakpoint to occur before the targeted instruction executes. This is possible because the PC breakpoint is
enabled when interrupt sampling occurs. For address and data breakpoints, reporting is considered
imprecise because several instructions may execute after the triggering address or data is detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception
processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for
multiple cycles. The core enters emulator mode when exception processing begins. After the standard
8-byte exception stack is created, the processor fetches a unique exception vector, 12, from the vector
table.
5-34
Theory of Operation
1
Encodings not shown are reserved for future use.
MCF5272 ColdFire
DDATA[3:0]/CSR[BSTAT]
Table 5-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
0000/0000
0010/0001
0100/0010
1010/0101
1100/0110
Table
®
Integrated Microprocessor User’s Manual, Rev. 3
5-21, when a breakpoint is triggered, an indication
1
No breakpoints enabled
Waiting for level-1 breakpoint
Level-1 breakpoint triggered
Waiting for level-2 breakpoint
Level-2 breakpoint triggered
Breakpoint Status
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