MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 168
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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System Integration Module (SIM)
6-8
30–27
15-11
Bits
31
26
25
24
23
22
21
20
19
18
17
16
TIMERPDN Timer power-down enable. Controls the clocking to the timer module.
UART1PDN UART1 power-down enable. Controls the clocking to the UART1 module. Clocking to the UART1
UART0PDN UART0 power-down enable. Controls the clocking to the UART0 module. Clocking to the UART0
DRAMPDN
ENETPDN
PWMPDN
GPIOPDN
QSPIPDN
BDMPDN
DMAPDN
USBPDN
PLIPDN
Field
—
—
Debug power-down enable. Controls the clocking to the debug module.
0 Clock enabled.
1 Clock disabled.
Reserved, should be cleared.
Ethernet power-down enable. Controls the clocking to the ethernet module.
0 Clock enabled.
1 Clock disabled.
PLIC power-down enable. Controls the clocking to the PLIC module.
0 Clock enabled.
1 Clock disabled.
DRAM controller power-down enable. Controls the clocking to the DRAM controller module.
0 Clock enabled.
1 Clock disabled.
DMA controller power-down enable. Controls the clocking to the DMA controller module.
0 Clock enabled.
1 Clock disabled.
PWM power-down enable. Controls the clocking to the PWM module.
0 Clock enabled.
1 Clock disabled.
QSPI power-down enable. Controls the clocking to the QSPI module.
0 Clock enabled.
1 Clock disabled.
0 Clock enabled.
1 Clock disabled.
Parallel port power-down enable. Controls the clocking to the parallel port module.
0 Clock enabled.
1 Clock disabled.
USB power-down enable. Controls the clocking to the USB module. Clocking to the USB module may
be turned on by USD_D+ or INT1/USB_WOR, at which time this bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
module may be restored when a change in signal level is detected on UART1RxD, at which time this
bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
module may be restored when a change in signal level is detected on UART0RxD, at which time this
bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
Reserved, should be cleared.
MCF5272 ColdFire
Table 6-5. PMR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Freescale Semiconductor
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