MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 388

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

UART Modules
Because the receiver is not active, received data cannot be read by the CPU and error status conditions are
inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they
are received. A received break is echoed as received until the next valid start bit is detected.
16.5.4
Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor
applications. In this mode, a master can transmit an address character followed by a block of data
characters targeted for one of up to 256 slave stations.
Although slave stations have their channel receivers disabled, they continuously monitor the master’s data
stream. When the master sends an address character, the slave receiver channel notifies its respective CPU
by setting USRn[RxRDY] and generating an interrupt (if programmed to do so). Each slave station CPU
then compares the received address to its station address and enables its receiver if it wishes to receive the
subsequent data characters or block of data from the master station. Slave stations not addressed continue
monitoring the data stream. Data fields in the data stream are separated by an address character. After a
slave receives a block of data, its CPU disables the receiver and repeats the process.Functional timing
information for multidrop mode is shown in
A character sent from the master station consists of a start bit, a programmed number of data bits, an
address/data (A/D) bit flag, and a programmed number of stop bits. A/D = 1 indicates an address character;
A/D = 0 indicates a data character. The polarity of A/D is selected through UMR1n[PT]. UMR1n should
be programmed before enabling the transmitter and loading the corresponding data bits into the transmit
buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it
is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the
receiver holding register FIFO stack provided the received A/D bit is a one (address tag). The character is
discarded if the received A/D bit is zero (data tag). If the receiver is enabled, all received characters are
transferred to the CPU through the receiver holding register stack during read operations.
In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the
status portion of the stack normally used for a parity error (USRn[PE]).
Detection of breaks and framing or overrun errors operates normally. The A/D bit replaces the parity bit,
so parity is neither calculated nor checked. Messages in this mode may still contain error detection and
correction information. If 8-bit characters are not required, software can be used to calculate parity and
append it to the 5-, 6-, or 7-bit character.
16-28
Multidrop Mode
MCF5272 ColdFire
CPU
Disabled
Disabled
Figure 16-29. Remote Loop-Back
®
Integrated Microprocessor User’s Manual, Rev. 3
Figure
Rx
Tx
16-30.
Disabled
Disabled
RxD Input
TxD Input
Freescale Semiconductor