MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 319

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

13.5.11 Aperiodic Status Register (PASR)
All bits in this register are read only and are set on hardware or software reset.
The PASR register is a 16-bit register containing the aperiodic interrupt status information for the C/I and
monitor channel transmit and receive registers for all four ports on the MCF5272. An aperiodic interrupt
condition remains asserted as long as any one of the bits within the PASR register is set.
Freescale Semiconductor
15, 11, 7, 3
14, 10, 6, 2
13, 9, 5, 1
12, 8, 4, 0
Bits
Reset
2
1
0
Bits
Field GCR
Addr
R/W
15
3
B2RDF
B1RDF
DRDF
Name
GCT
GMRn
Name
GCRn
GCTn
GMTn
14
3
D receive data full. This bit indicates that the D receive data register for the respective port is full.
DRDF is cleared when the CPU reads the receive data register PnDRR.
B2 receive data full. This bit indicates that the B2 receive data register for the respective port is full.
B2RDF is cleared when the CPU reads the receive data register PnB2RR.
B1 receive data full. This bit indicates that the B1 receive data register for the respective port is full.
B1RDF is cleared when the CPU reads the receive data register PnB2RR.
GMR
MCF5272 ColdFire
13
3
GCI C/I received. When set, this bit indicates that valid new data has been written to a GCI C/I
receive register. An interrupt is queued when this bit is set if the GCR interrupt enable bit has
been set in the corresponding PnICR register. The GCR bit and associated interrupt are
automatically cleared when the corresponding PnGCIR register has been read by the CPU.
GCI C/I transmitted. When set, this bit indicates that a C/I register is empty. An interrupt is
queued when this bit is set if the GCT interrupt enable bit has been set in the corresponding
PnICR register. The GCT bit and associated interrupt are automatically cleared when the
PGCITSR register has been read by the CPU.
GCI monitor received. When set, this bit indicates that data has been written to a monitor
channel receive register. An interrupt is queued when this bit is set if the GMR interrupt enable
bit has been set in the corresponding PnICR register. The GMR bit and associated interrupt are
automatically cleared when the corresponding PnGMR register has been read by the CPU.
GCI monitor transmitted. When set, this bit indicates that the monitor channel transmit register
is empty. An interrupt is queued when this bit is set if the GMT interrupt enable bit has been set
in the corresponding PnICR register. The GMT bit and associated interrupt are automatically
cleared when the PGMTS register has been read by the CPU.
GMT
12
3
Figure 13-23. Aperiodic Status Register (PASR)
Table 13-5. P0PSR–P3PSR Field Descriptions
GCR
11
Table 13-6. PASR Field Descriptions
2
®
GCT
Integrated Microprocessor User’s Manual, Rev. 3
10
2
GMR
0000_0000_0000_0000
2
9
MBAR + 0x38C
GMT
Read Only
8
2
GCR
Description
1
7
Description
GCT
1
6
GMR
5
1
Physical Layer Interface Controller (PLIC)
GMT
1
4
GCR
0
3
GCT
2
0
GMR
0
1
GMT
0
0
13-23