MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 369

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

16.3.5
The UART command registers (UCRn),
commands that do not conflict can be specified in a single write to a UCRn. For example,
TRANSMITTER
Table 16-6
Operating
Freescale Semiconductor
Bits
6–4
7
ENAB
Value
000
001
010
011
100
101
110
111
Modes,” show how these commands are used.
describes UCRn fields and commands. Examples in
UART Command Registers (UCRn)
Address
no command
reset mode register
pointer
reset receiver
reset transmitter
reset error status
reset break– change
interrupt
start break
stop break
and
Reset
Field
R/W
Command
ENABLE TRANSMITTER
MCF5272 ColdFire
—
ENAB
7
Figure 16-6. UART Command Registers (UCRn)
Enable autobaud
0 Autobaud disabled.
1 Autobaud enabled. The transmission rate is calculated from the first received
—
Causes the mode register pointer to point to UMR1n.
Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes the
receiver FIFO pointer. No other registers are altered. Because it places the receiver in
a known state, use this command instead of
receiver.
Disables the transmitter and clears USRn[TxEMP,TxRDY]. No other registers are
altered. Because it places the transmitter in a known state, use this command instead
of
Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after a data
block is received.
Clears the delta break bit, UISRn[DB].
Forces TxD low. If the transmitter is empty, the break may be delayed up to one bit time.
If the transmitter is active, the break starts when character transmission completes. The
break is delayed until any character in the transmitter shift register is sent. Any character
in the transmitter holding register is sent after the break. The transmitter must be
enabled for the command to be accepted. This command ignores the state of CTS.
Causes TxD to go high (mark) within two bit times. Any characters in the transmitter
buffer are sent.
6
Table 16-6. UCRn Field Descriptions
MISC Field (This field selects a single command.)
TRANSMITTER DISABLE
character. If the rate must be recalculated, ENAB must first be cleared and reset.
UISRn[ABC] indicates a transmission rate has been calculated and loaded into the
UART divider registers. UDUn and UDULn must be initialized to 0x00 before enabling
autobaud.
®
Integrated Microprocessor User’s Manual, Rev. 3
Figure
MISC
cannot be specified in one write.
MBAR + 0x108, 0x148
16-6, supply commands to the UART. Only multiple
4
0000_0000
Write only
when reconfiguring the transmitter.
3
Section 16.5.2, “Transmitter and Receiver
Description
TC
2
RECEIVER DISABLE
1
RC
when reconfiguring the
0
RESET
UART Modules
16-9