MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 15

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Paragraph
Number
4.1 Interactions between Local Memory Modules .............................................................................. 4-1
4.2 Local Memory Registers ................................................................................................................ 4-2
4.3 SRAM Overview ........................................................................................................................... 4-2
4.4 ROM Overview .............................................................................................................................. 4-5
4.5 Instruction Cache Overview .......................................................................................................... 4-7
5.1 Overview ........................................................................................................................................ 5-1
5.2 Signal Description .......................................................................................................................... 5-2
5.3 Real-Time Trace Support ............................................................................................................... 5-3
5.4 Programming Model ...................................................................................................................... 5-5
Freescale Semiconductor
4.3.1 SRAM Operation ................................................................................................................ 4-2
4.3.2 SRAM Programming Model .............................................................................................. 4-2
4.4.1 ROM Operation .................................................................................................................. 4-5
4.4.2 ROM Programming Model ................................................................................................. 4-5
4.5.1 Instruction Cache Physical Organization ........................................................................... 4-7
4.5.2 Instruction Cache Operation ............................................................................................... 4-8
4.5.3 Instruction Cache Programming Model ........................................................................... 4-12
5.3.1 Begin Execution of Taken Branch (PST = 0x5) ................................................................. 5-4
5.4.1 Revision A Shared Debug Resources ................................................................................. 5-7
5.4.2 Address Attribute Trigger Register (AATR) ...................................................................... 5-7
5.4.3 Address Breakpoint Registers (ABLR, ABHR) ................................................................. 5-9
5.4.4 Configuration/Status Register (CSR) ............................................................................... 5-10
4.3.2.1 SRAM Base Address Register (RAMBAR) ......................................................... 4-3
4.3.2.2 SRAM Initialization ............................................................................................. 4-4
4.3.2.3 Programming RAMBAR for Power Management ............................................... 4-4
4.4.2.1 ROM Base Address Register (ROMBAR) ........................................................... 4-5
4.4.2.2 Programming ROMBAR for Power Management ............................................... 4-6
4.5.2.1 Interaction with Other Modules ............................................................................ 4-8
4.5.2.2 Cache Coherency and Invalidation ....................................................................... 4-8
4.5.2.3 Caching Modes ..................................................................................................... 4-9
4.5.2.4 Reset ................................................................................................................... 4-10
4.5.2.5 Cache Miss Fetch Algorithm/Line Fills ............................................................. 4-10
4.5.3.1 Cache Control Register (CACR) ........................................................................ 4-12
4.5.3.2 Access Control Registers (ACR0 and ACR1) .................................................... 4-14
4.5.2.3.1 Cacheable Accesses ..................................................................................... 4-9
4.5.2.3.2 Cache-Inhibited Accesses ............................................................................ 4-9
MCF5272 ColdFire
Table of Contents (Continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Debug Support
Local Memory
Chapter 4
Chapter 5
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