MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 105

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

4.3.2.1
RAMBAR determines the base address location of the internal SRAM module, as well as the definition of
the types of accesses allowed for it.
RAMBAR fields are described in
Freescale Semiconductor
•
•
Address
31–12
11–9
Bits
7–6
5–1
Reset
8
0
RAMBAR is a 32-bit write-only supervisor control register. It is accessed in the CPU address space
via the MOVEC instruction with an Rc encoding of 0xC04. RAMBAR can be read or written in
background debug mode (BDM). At system reset, the V bit is cleared and the remaining bits are
uninitialized. To access the SRAM module, RAMBAR must be written with the appropriate base
address after system reset.
The SRAM base address register (RAMBAR) can be accessed only in supervisor mode using the
MOVEC instruction with an Rc value of 0xC04.
Field
R/W
UC, UD
Name
WP
C/I,
SC,
SD,
31
SRAM Base Address Register (RAMBAR)
BA
—
—
V
Base address. SRAM module base address. The SRAM module occupies a 4-Kbyte space defined
by BA. SRAM can reside on any 4-Kbyte boundary in the 4-Gbyte address space.
Reserved, should be cleared.
Write protect. Controls read/write properties of the SRAM.
0 Allows read and write accesses to the SRAM module.
1 Allows only read accesses to the SRAM module. Any attempted write reference generates an
Reserved, should be cleared.
Address space masks (ASn). These fields allow certain types of accesses to be masked, or inhibited
from accessing the SRAM module. These bits are useful for power management as described in
Section 4.3.2.3, “Programming RAMBAR for Power
The address space mask bits are follows:
C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each ASn bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. References to this address space cannot
Valid. Enables/disables the SRAM module. V is cleared at reset.
0 RAMBAR contents are not valid.
1 RAMBAR contents are valid.
access error exception to the ColdFire processor core.
access the SRAM module and are processed like other non-SRAM references.
MCF5272 ColdFire
Figure 4-1. SRAM Base Address Register (RAMBAR)
BA
Table
Table 4-2. RAMBAR Field Description
®
Integrated Microprocessor User’s Manual, Rev. 3
4-2.
W for CPU; R/W for debug
CPU space + 0xC04
—
Description
12 11
—
Management.” In particular, C/I is typically set.
9
WP
8
7
—
6
C/I SC SD UC UD V
5
4
3
2
Local Memory
1
0
0
4-3