MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 446

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
19.17.3 Test and Debug Data Out (TDO/DSO)
JTAG mode: The TDO output is for shifting data out of the serial data port logic. Shifting out of data
depends on the state of the JTAG controller state machine and the instructions currently in the instruction
register. This data shift occurs on the falling edge of TCK. When TDO is not outputting data it is placed
in a high-impedance state. TDO can also be three-stated to allow bussed or parallel connections to other
devices having JTAG test access ports.
BDM mode: DSO is the debug data output.
19.17.4 Test and Debug Data In (TDI/DSI)
JTAG mode: The TDI input is for loading the serial data port shift registers (boundary scan registers,
bypass register and instruction register). Shifting in of data depends on the state of the JTAG controller
state machine and the instruction currently in the instruction register. Data is shifted in on the rising edge
of TCK.
BDM mode: DSI is the debug serial data input. This signal requires a 10-K¾ pullup resistor.
19.17.5 JTAG TRST and BDM Data Clock (TRST/DSCLK)
JTAG mode: TRST asynchronously resets the JTAG TAP logic when low.
BDM mode: DSCLK is the BDM serial data clock input. It requires a 10-K¾ pullup resistor.
19.17.6 Freescale Test Mode Select (MTMOD)
MTMOD: When the MTMOD input is low, JTAG mode is enabled. When it is high, BDM mode is
enabled.
19.17.7 Debug Transfer Error Acknowledge (TEA)
An external slave asserts the TEA input to indicate an error condition for the current bus transfer. It is
provided to allow full debug port capability. The assertion of TEA causes the MCF5272 to abort the
current bus cycle. If a 10-K¾ pullup resistor is not connected, external logic must drive TEA high when it
is inactive. TEA has no effect during SDRAM accesses. If high parasitic capacitance occurs on the printed
circuit board, a lower value pullup resistor may be needed.
19.17.8 Processor Status Outputs (PST[3:0])
PST[3:0] outputs indicate core status, as shown in
Table
19-7. Debug mode timing is synchronous with
the processor clock; status is unrelated to the current bus transfer.
®
MCF5272 ColdFire
Integrated Microprocessor User’s Manual, Rev. 3
19-36
Freescale Semiconductor