MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 286

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Universal Serial Bus (USB)
12.3.2.19 USB Endpoint 0–7 Data Present Registers (EPnDPR)
Figure 12-22
with external devices to prevent data loss (overwrite) says how much free space is still available. Gives
amount of data just received.
Table 12-18
12.3.3
The USB module supports up to 1 KByte of USB descriptors. The configuration RAM begins at address
MBAR + 0x1400 and is longword accessible only. EPCTL0[CFG_RAM_VAL] must be cleared to access
the configuration RAM, otherwise an access error results.
12.3.3.1
The USB host must configure a device before that device’s function can be used. The host configures the
device by first reading the descriptors for the device. The descriptors must follow the format described in
Chapter 9 of the USB specification and any relevant class specification.
12-28
Reset
Field
Addr
R/W
15–9
Bits
8–0
15
Configuration RAM
describes EPDPn fields.
Configuration RAM Content
shows the USB endpoint 0-7 data present registers. used to coordinate user access to FIFO
Name
DATA_PRES Endpoint n data present. This field reflects the number of bytes in the endpoint’s FIFO. This field
The USB descriptors use little endian format for word and longword fields.
The MCF5272 uses big endian format for words and longwords. The user
must make sure that any word or longword fields are stored in the correct
byte order.
—
Figure 12-22. USB Endpoint 0-7 Data Present Registers
MCF5272 ColdFire
MBAR + 0x10CE, 0x10D2, 0x10D6, 0x10DA, 0x10DE, 0x10E2, 0x10E6, 0x10EA
Description
Reserved, should be cleared.
is updated when the user writes to or reads from the FIFO and when the control logic accesses
the FIFO. For non-isochronous endpoints, the FIFO level is only updated when a complete
packet is received or transmitted without any errors. This occurs synchronously with an EOP
interrupt. For isochronous endpoints, the FIFO level is updated by the control logic in real-time
rather than only after the transfer of a complete packet.
Note: for non-isochronous OUT endpoints, this field is frozen while an EOT interrupt is pending
in order to allow the user to determine the number of bytes to read for the last transfer. For
endpoint 0, EPDP0 monitors the OUT FIFO only.
—
Table 12-18. EP
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_0000
9
n
NOTE
DPR Field Descriptions
8
Read
DATA_PRES
(
EP
n
DPR)
Freescale Semiconductor
0