MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 85

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
MOVE from
MAC
MOVE to
MAC
MOVE from
CCR
MOVE to
CCR
MOVEA
MOVEM
MOVEQ
MSAC
MSACL
MULS
MULU
NEG
NEGX
NOP
NOT
OR
ORI
PEA
PULSE
REMS
REMU
RTS
Scc
Instruction
MASK,Rx
ACC,Rx
MACSR,Rx
MACSR,CCR
Ry,ACC
Ry,MACSR
Ry,MASK
#<data>,ACC
#<data>,MACSR
#<data>,MASK
CCR,Dx
Dy,CCR
#<data>,CCR
<ea>y,Ax
#<list>,<ea-2>x
<ea-2>y,#<list>
#<data>,Dx
Ry,RxSF
Ry,RxSF,<ea-1>y,Rw
<ea>y,Dx
<ea>y,Dx
Dx
Dx
none
Dx
<ea>y,Dx
Dy,<ea>x
#<data>,Dx
<ea-3>y
none
<ea-1>,Dx
<ea-1>,Dx
none
Dx
Operand Syntax
MCF5272 ColdFire
Table 2-7. User-Mode Instruction Set Summary (continued)
.L
.L
.L
.L
.W
.B
.W,.L → .L
.L
.L
.B → .L
.L - (.W × .W) → .L
.L - (.L × .L) → .L
.L - (.W × .W) → .L, .L
.L - (.L × .L) → .L, .L
.W X .W → .L
.L X .L → .L
.W X .W → .L
.L X .L → .L
.L
.L
Unsized
.L
.L
.L
.L
Unsized
.L
.L
Unsized
.B
Operand Size
®
Integrated Microprocessor User’s Manual, Rev. 3
Rm → Rx
MACSR → CCR
Ry → Rm
#<data> → Rm
CCR → Dx
Dy → CCR
#<data> → CCR
Source → destination
Listed registers → destination
Source → listed registers
Sign-extended immediate data → destination
ACC – (Ry × Rx){<< 1 | >> 1} → ACC
ACC – (Ry × Rx){<< 1 | >> 1} → ACC;
(<ea-1>y{&MASK}) → Rw
Source × destination → destination
Signed operation
Source × destination → destination
Unsigned operation
0 – destination → destination
0 – destination – X → destination
Synchronize pipelines; PC + 2 → PC
~ Destination → destination
Source | destination → destination
Immediate data | destination → destination
SP – 4 → SP; Address of <ea> → (SP)
Set PST= 0x4
Dx/<ea>y → Dw {32-bit remainder}
Signed operation
Dx/<ea>y → Dw {32-bit remainder}
Unsigned operation
(SP) → PC; SP + 4 → SP
If condition true, then 1s ⎯ destination;
Else 0s → destination
Operation
ColdFire Core
2-17