MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 306

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Physical Layer Interface Controller (PLIC)
Note that only the active, that is enabled, B- and D-channel receive and transmit registers need to be read
and written. B and D channels which are not active need not have their receive and transmit registers read
and written.
It should be clear from
frame (n) is written to the PLIC transmit register during the interrupt service routine of the previous frame,
frame (n-1). Similarly on the receive side, frame (n) is read from the PLIC receive register during the
interrupt service routine of the following frame, frame (n + 2).
delay through the PLIC, when not in loopback mode, is two 2-KHz frames, or 1 mS.
13.2.5.2
The aperiodic status interrupt is an interrupt which is driven by a number of conditions. The CPU services
this interrupt by reading the aperiodic status register, ASR, and by reading or writing the relevant C/I or
monitor channel register or registers which have generated this interrupt. Once read, the interrupt is
cleared. Each port and individual interrupts within each port is maskable. The following conditions for
each of the ports can trigger this interrupt:
13-10
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•
•
•
Slot 0
125 μs
2-KHz interrupt
Monitor channel receive: ASR defines which port or ports have generated a monitor channel
receive interrupt. The interrupt service routine must then read the appropriate GMR register or
registers to clear the monitor channel receive interrupt.
Monitor channel transmit: ASR defines which port or ports have generated a monitor channel
transmit interrupt. The interrupt service routine must then read the appropriate GMT register or
registers to clear the monitor channel transmit interrupt.
C/I channel receive: ASR defines which port or ports have generated a C/I channel receive
interrupt. The interrupt service routine must then read the appropriate GCIR register or registers to
clear the C/I channel receive interrupt.
C/I channel transmit: ASR defines which port or ports have generated a C/I channel transmit
interrupt. The interrupt service routine must then read the appropriate GCIT register or registers to
clear the C/I channel transmit interrupt.
Read Frame n -1 (B&D)
Write Frame n + 1 (B&D)
Interrupt service routine
GCI Aperiodic Status Interrupt
Slot 1
Frame n
500 μs
MCF5272 ColdFire
Figure 13-10
Slot 2
Slot 3
Figure 13-10. Periodic Frame Interrupt
that due to the double buffering through the PLIC shadow register,
®
Integrated Microprocessor User’s Manual, Rev. 3
2-KHz interrupt
Slot 0
Interrupt service routine
Read Frame n (B&D)
Write Frame n + 2 (B&D)
Slot 1
Frame n + 1
Slot 2
Figure 13-10
Slot 3
2-KHz interrupt
Slot 0
shows that the minimum
Interrupt service routine
Read Frame n + 1 (B&D)
Write Frame n + 3 (B&D)
Frame n + 2
Slot 1
Freescale Semiconductor
Slot 2