MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 473
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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20.12.4 Soft Reset Operation
If the soft reset bit, SCR[SOFTRST], is programmed to generate a reset, RSTO is asserted for 128 clocks,
resetting all external devices as with a normal or master reset. All internal peripherals with the exception
of the SIM, chip select, interrupt controller, GPIO module, and SDRAM controller are reset also. The
SDRAM controller is reset only when DRESETEN is tied low.
SCR[SOFTRST] is automatically cleared at the end of the 128 clock period. Software can monitor this bit
to determine the end of the soft reset.
SCR[SOFTRST].
During the soft reset period, all bus signals continue to operate normally.
Freescale Semiconductor
CLKIN
SoftRST
RSTO
INTERNAL
PERIPHERALS
RSTI
The levels of the mode pins are not sampled during a software watchdog
reset. If the port size and acknowledge features of CS0 are different from the
values programmed in CSBR0 and CSOR0 at the time of the software
watchdog reset, you must assert RSTI during software watchdog reset to
cause the mode pins to be resampled.
Like the normal reset, the soft reset does not reset the SDRAM controller
unless DRESETEN is asserted during the reset. When DRESETEN is
negated, SDRAM refreshes continue to be generated during and after reset
at the programmed rate and with the programmed waveform timing.
MCF5272 ColdFire
Figure 20-24. Soft Reset Timing
Figure 20-24
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
NOTE
shows the timing of RSTO when asserted by
CLK CYCLES
T = 128
Bus Operation
20-25
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