MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 469

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

20.11 Bus Arbitration
The MCF5272 does not allow external bus masters. There are three on-chip bus masters. These are the
ColdFire core, the Fast Ethernet Controller, and the memory-to-memory DMA Controller.
20.12 Reset Operation
The MCF5272 supports four types of reset, two of which are external hardware resets (master reset and
normal reset), a soft reset, which is generated by setting SCR[SOFTRST], and the software watchdog
reset.
There are two reset input pins, RSTI and DRESETEN. When DRESETEN is asserted, any of the reset
sources reset the SDRAM controller. When DRESETEN is negated, the SDRAM controller is not reset.
This is useful during software debugging since it is preferable to retain SDRAM data in the case of
catastrophic system failure. In a production system, if may be preferable to tie DRESETEN low.
Master reset resets the entire MCF5272 including the SDRAM controller. Master reset occurs when both
RSTI and DRESETEN are asserted simultaneously. This is the reset that should be applied to the
MCF5272 device at power up.
Normal reset resets all of the MCF5272 with the exception of the SDRAM controller. Normal reset occurs
when RSTI is asserted and DRESETEN is negated. Normal reset allows DRAM refresh cycles to continue
at the programmed rate and with the programmed waveform timing while the remainder of the system is
being reset, maintaining the data stored in DRAM.
SCR[SOFTRST] resets all on-chip peripherals and devices connected to RSTO. It resets the SDRAM
controller only when DRESETEN is asserted.
The software watchdog reset acts as an internally generated normal reset when DRESETEN is negated. It
resets the SDRAM controller only when DRESETEN is asserted.
Freescale Semiconductor
TEA normally should be asserted for no more than three CLKIN periods.
The minimum is two clock periods.
TEA is internally synchronized on the rising edge of CLKIN. Depending on
when this synchronization takes place, the Cx cycle may not occur.
Master reset must be asserted for all power-on resets. This is done by driving
RSTI and DRESETEN low simultaneously. Failure to assert master reset
during power-on sequences results in unpredictable DRAM controller
behavior.
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
NOTE
NOTE
Bus Operation
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