MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 301

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

13.2.3
Unencoded voice is normally presented on the physical line most significant bit first (left aligned). See the
MC145484 data sheet for an example. Accordingly, the MCF5272 normally assumes incoming data are
left-aligned.
However, this convention is reversed when the data stream is HDLC (high-level data link control)
encoded. HDLC-stuffing and unstuffing are done by counting bits from the lsb. The look-up table in the
software HDLC on this device transmits the lsb first.
13.2.3.1
Because unencoded voice data appears on the physical interface most significant bit (msb) first, the msb
is left aligned in the transmit and receive shift register; that is, the first bit of B-channel received data is
aligned in the msb position as shown in
The CPU uses longword (32-bit) registers (like P0B1RR) to communicate B-channel data to/from the
PLIC. These registers are loaded by concatenating four of the 8-bit/8-KHz frames. The four frames are
aligned sequentially as shown in
position, and the fourth frame taking the least significant byte (LSB) position. See
Data Receive Registers
(P0B2TR–P3B2TR),” for more information about some of these registers.
Freescale Semiconductor
Shadow Register
B1, B2 Transmit
Data Register
GCI/IDL B- and D-Channel Bit Alignment
B-Channel Unencoded Data
MCF5272 ColdFire
START
Figure 13-5. GCI/IDL B Data Transmit Register Multiplexing
(P0B1RR–P3B1RR),” or
8 bits
Figure
®
Integrated Microprocessor User’s Manual, Rev. 3
Figure
13-6, with the first frame in the most significant byte (MSB)
8 bits
13-6.
Shift Register
Section 13.5.5, “B2 Data Transmit Registers
32 bits
8 bits
MUX
32
32
8 bits
2-KHz transfer and interrupt
Physical Layer Interface Controller (PLIC)
8-KHz Rate
Internal Bus
8 bits
Section 13.5.1, “B1
END
13-5