MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 177

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Chapter 2, “ColdFire
ICRs.
For an interrupt to be successfully processed, stack RAM must be available. A programmable chip select
is often used for the RAM, in which case, the RAM is not immediately available at startup. Thus, no
interrupts are recognized until PIVR is initialized. The RAM chip select and system stack should be set up
before this initialization.
If more than one interrupt source has the same interrupt priority level (IPL), the interrupt controller daisy
chains the interrupts with the priority order following the bit placement in the PIWR, with INT1 having
the highest priority and SWTO having the lowest priority, as shown in
7.2.1
This section describes the registers associated with the interrupt controller.
nomenclature used for the interrupt and power management registers.
Freescale Semiconductor
INT1, INT2, INT3, INT4, INT5, INT6
TMR0, TMR1, TMR2, TMR3
USB0, USB1, USB2, USB3, USB4, USB5,
USB6, USB7
UART1, UART2
PLIP
PLIA
DMA
ETx
ERx
ENTC
QSPI
IPL2, IPL1, IPL0
PI
PDN
WK
SWTO
Interrupt Controller Registers
Mnemonic or Portion Thereof
Table 7-2. Interrupt and Power Management Register Mnemonics
Core.” Pending interrupts from external sources (INT[6:1]) can be cleared using the
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
External interrupt signals 1–6.
Timers 3–0 from timer module
USB endpoint 0–7
UART1, UART2 modules
PLIC 2-KHz periodic interrupt, 2B+D data
PLIC asynchronous and maintenance channels interrupt
DMA controller interrupt
Ethernet module transmit data interrupt
Ethernet module receive data interrupt
Ethernet module non-time-critical interrupt
Queued serial peripheral interface
Interrupt priority level bits 2–0
Pending interrupt
Power down enable
Wakeup enable
Software watchdog timer time out
Description
Figure
Table 7-2
7-8.
gives the
Interrupt Controller
7-3