MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 188

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Chip Select Module
Table 8-3
8-4
Bits
4–2
1
0
ENABLE Enable. Disables/enables the chip select. When disabled, the chip select is never asserted, regardless of
Name
describes the interaction between CSBRn[EBI], OE/RD, R/W, and SDWE.
CTM
TM
The MCF5272 compares the address for the current bus transfer with the
address and mask bits in the CSBRs and CSORs looking for a match. The
priority is listed in
Table 8-3. Output Read/Write Strobe Levels versus Chip Select EBI Code
Transfer modifier. Operates with TT to determine the access type.
TT
0x
0x
0x
0x
0x
0x
0x
10
10
10
10
11
11
11
11
11
11
11
11
Compare TM. Enables comparison between the access type and the TM and TT bits.
0 TT and TM register bits do not affect address match.
1 TT and TM register bits must match the access type for an address match to occur.
the address on the internal bus. ENABLE is 0 at reset, except CS0 which is 1.
0 Chip select is disabled, no matches can occur and chip select output cannot assert.
1 Chip select is enabled, bus cycles are compared against register contents.
EBI
00
01
11
MCF5272 ColdFire
TM
000
001
010
011–100
101
110
111
000–100
101
110
111
000
001
010
011
100
101
110
111
EBI Function
SRAM, ROM
SRAM, ROM
Table 8-2. CSBRn Field Descriptions (continued)
SDRAM
Table 8-4
Function
Reserved
User data access
User instruction access
Reserved
Supervisor data access
Supervisor instruction access
Reserved
Reserved
Emulator mode data access
Emulator mode instruction access
Reserved
CPU space access
Interrupt acknowledge level 1
Interrupt acknowledge level 2
Interrupt acknowledge level 3
Interrupt acknowledge level 4
Interrupt acknowledge level 5
Interrupt acknowledge level 6
Interrupt acknowledge level 7
®
Integrated Microprocessor User’s Manual, Rev. 3
Access Type
(from highest priority to lowest priority):
Write
Read
Write
Read
Write
Read
NOTE
Description
OE/RD
High
High
High
High
Low
Low
High
High
High
High
R/W
Low
Low
SDWE
High
High
High
High
High
Low
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