MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 532

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Index
Device identification register,
DMA
Documentation,
DSCLK,
E
Electrical specifications
Ethernet
Index-2
breakpoint operation,
module enhancements,
real-time support,
taken branch,
theory,
address modes,
byte count register,
controller registers,
data transfer types,
destination address register,
interrupt register,
mode register,
source address register,
AC,
AC timing
clock input and output timing,
DC,
DL and GCI interface timing,
maximum ratings,
MII async inputs signal timing,
operating temperature,
output loading,
processor bus input timing,
QSPI, 23-31,
SDRAM interface timing,
supply, input voltage, and storage temperature,
thermal resistance,
timer module AC timing,
USART module AC timing,
address recognition,
buffer descriptors
CAM interface,
collision handling,
control register,
descriptor active register,
descriptor ring register
error handling,
debug,
fast Ethernet,
GPIO port,
IEEE 1149.1 (JTAG),
USB interface,
receive,
transmit,
pointer-to-receive,
pointer-to-transmit,
23-5
23-3
5-2
5-34
23-13
11-35
11-37
23-32
23-28
5-4
1-xliii
10-2
11-9
23-3
10-2
23-17
11-6
11-11
23-29
10-4
5-33
23-1
23-2
11-8
10-1
10-6
10-2
11-6
11-30
5-34
11-31
23-2
2-4
10-5
MCF5272 ColdFire
23-30
23-21
11-15
23-14
23-6
6-11
10-6
23-22
23-23
23-5
23-19
®
Integrated Microprocessor User’s Manual, Rev. 3
23-1
Exception processing
Exceptions
Execution timings
External bus interface overview,
F
Fault-on-fault halt,
Features overview,
Frame reception,
FEC initialization,
FIFO
frame
hardware initialization,
hash table
initialization sequence,
internal and external loopback,
interpacket gap time,
interrupt
loopbacks,
maximum frame length register,
MII
module operation,
programming model,
RAM perfect match address register
receive buffer size register,
receive control register,
transceiver connection,
transmit
user initialization,
overview,
processor exceptions,
stack frame definition,
bus,
miscellaneous,
one operand,
two operands,
receive bound register,
receive start register,
transmit start register,
reception,
transmission,
algorithm,
high register,
low register,
event register,
mask register,
vector status register,
management frame register,
speed control register,
high,
low,
control register,
descriptor active register,
FIFO watermark,
20-3
11-26
11-27
2-25
11-8
11-5
11-8
2-22
2-22
11-5
11-29
2-24
11-4
11-28
11-13
11-12
5-16
1-1
11-25
11-33
11-1
11-34
11-21
11-8
11-10
2-28
2-27
11-33
11-20
11-33
11-3
11-14
11-23
11-22
11-18
11-19
11-32
11-16
11-17
1-5
11-8
11-24
Freescale Semiconductor