MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 404

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

General Purpose I/O Module
17.3
These registers are used to program GPIO port signals as inputs or outputs. The data direction bit for any
line is ignored unless that line is configured for general purpose I/O in the appropriate control register. If
a GPIO line changes from an input to an output, the initial data on that pin is the last data written to the
latch by the corresponding data register.
At system reset, these register bits are all cleared, configuring all port I/O lines as general purpose inputs.
Bootstrap software must write an appropriate value into the data direction register to configure GPIO port
signals as outputs. When these registers are first written, any internal pullups on the corresponding I/O pins
are disabled.
A detailed description is provided only for data direction register A (PADDR). The control bits in all three
registers operate in the same manner.
17.3.1
The PADDR determines the signal direction of each parallel port pin programmed as a GPIO port in the
PACNT.
17.3.2
The PBDDR determines the signal direction of each parallel port pin programmed as a GPIO port in the
PBCNT.
17-10
15–0
Bits
Reset
Reset
Field
Field
Addr
Addr
R/W
R/W
Data Direction Registers
15
15
Port A Data Direction Register (PADDR)
Port B Data Direction Register (PBDDR)
PADDR
Name
MCF5272 ColdFire
Data direction bits. Each data direction bit selects the direction of the signal as follows:
0 Signal is defined as an input.
1 Signal is defined as an output.
Figure 17-5. Port B Data Direction Register (PBDDR)
Figure 17-4. Port A Data Direction Register (PADDR)
Table 17-9. PADDR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x008C
MBAR + 0x0084
Read/Write
Read/Write
PBDDR
PADDR
Description
Freescale Semiconductor
0
0