MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 342

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Peripheral Interface (QSPI) Module
The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap register
(QWR):
The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the
following sequence repeats:
Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each
command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs,
QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables
wraparound mode.
QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless
another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to
show the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be written
at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a
transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and
QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.
Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations of phase
and polarity using QMR[CPHA, CPOL]. Data is transferred most significant bit (msb) first. The number
of bits transferred defaults to eight, but can be set to any value from 8 to 16 by writing a value into the
BITSE field of the command RAM, QCR[BITSE] .
14.4.1
The QSPI contains an 80-byte block of static RAM that can be accessed by both the user and the QSPI.
This RAM does not appear in the MCF5272 memory map because it can only be accessed by the user
indirectly through the QSPI address register (QAR) and the QSPI data register (QDR). The RAM is
divided into three segments with 16 addresses each:
The transmit and command RAM are write-only by the user. The receive RAM is read-only by the user.
Figure 14-2
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate
locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes of commands.
14-4
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1. The command pointed to by the internal pointer is executed.
2. The value in the internal pointer is copied into QWR[CPTQP].
3. The internal pointer is incremented.
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The new queue pointer, QWR[NEWQP], points to the first command in the queue.
An internal queue pointer points to the command currently being executed.
The completed queue pointer, QWR[CPTQP], points to the last command executed.
The end queue pointer, QWR[ENDQP], points to the final command in the queue.
receive data RAM, the initial destination for all incoming data
transmit data RAM, a buffer for all out-bound data
command RAM, where commands are loaded
QSPI RAM
shows the RAM configuration. The RAM contents are undefined immediately after a reset.
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor