cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 95

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.3.3
2.3.4
500028C
UTOPIA Parity
UTOPIA Multi-PHY Operation
The CX2836x supports even and odd parity, which is selected by OddEven, bit 2, in
the UTOP1 register (0x0D). The parity on received data is generated for either 8 bits
or 16 bits, according to the selected bus width in bit 0 of the MODE register (0x0202).
The result is output on URxPrty (pin V14).
Likewise, the parity on transmitted data is checked for either 8 bits or 16 bits,
according to the selected bus width. The calculated result should match the bit present
on UTxPrty (pin W11). If it does not match, a parity error has occurred. This error can
be observed either in the ParErr bit (bit 7) in the TXCELL register (0x2E) or in the
ParErrInt bit (bit 7) in the TXCELLINT register (0x2C). Systems that do not use
parity should disable the generation of interrupts caused by parity errors by writing bit
7 of the ENCELLT register (0x28) to 0.
The CX2836x supports multi-PHY operation as described in the UTOPIA Level
specification (af-phy-0039.000, see http://www.atmforum.com). Three primary
functions are involved in this operation: polling, selection, and data transfer. These
functions are basically the same for both the transmit and receive sides of the
UTOPIA bus. The following example describes the transmit functions.
The ATM layer UTOPIA controller polls the connected PHY ports by transmitting the
port addresses on the UTxAddr lines. If a port is ready to transfer data, it asserts
UTxCLAV . The controller determines which port is to transfer data and selects that
port by transmitting its address. The controller then asserts UTxEnb* to allow the
PHY to transfer data on the UTxData lines. UTxEnb* is deasserted when the transfer
is completed. Polling can continue during the data transfer process but not during port
selection. It operates independently of the state of UTxEnb*.
To pause the data transfer, UTxEnb* can be deasserted. To continue the transfer, the
controller must reselect the port by transmitting its address one clock cycle before
asserting UTxEnb*. The controller must ensure that the cell transfer from this port has
been completed, to avoid a start-of-cell error.
The CX2836x has a UTOPIA receiver output disable feature which allows the user to
set up redundant or back-up PHYs with the same UTOPIA address on the same
UTOPIA bus. In this setup, both PHYs’ transmitters are enabled, sending out identical
data streams. Both PHYs’ receivers are enabled, but only one is transferring data to
the ATM device. The receiver output is disabled in the backup PHY by writing the
UtopDis, bit 5, in the UTOP2 register (0x0E) to a logical 1. This disable places five of
the backup PHY’s signals, URxData, URxPrty, URxSOC, URxCLAV , and UTxCLAV ,
in a high-impedance state, preventing data and control signals from being passed to
the ATM layer device. The disabled receiver flushes its FIFO buffers at the same rate
as the enabled one, but all data it has received, except the last four cells, is lost. If the
primary PHY device encounters an unacceptable error rate, software quickly enables
the backup PHY and disables the primary PHY, reducing cell loss in the transition.
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
To facilitate multi-PHY operation, the CX2836x assigns a different address to each of
its twelve ports by default.
Functional Description
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