cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 156

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x26—CR06 (Feature3 Control Register)
PayldLp
RlineLp
TxFEACIE
FEACSin
RxFEACSNEIE
RxFEACIdleIE
RxFEACIE
3-46
PayldLp
7
Payload Loopback Enable—Set to enable a payload loopback from the receiver circuit through
the transmitter circuit back to the network. This loopback connects the received payload (after
decoding, frame recovery and overhead extraction) to the transmitter input, where it is framed
and encoded again. The received data is still present on the receiver output pins. A dynamic
change of this bit can cause loss of data for a few clock cycles, until the channel is internally
synchronized. Activation or deactivation of a loopback causes internal circuits to switch
between clocks. After writing to this bit the microprocessor should not access any of the device
registers (read/write) for 20 slowest clock cycles.
Remote Line Loopback Enable—Set to enable loopback after decoding or encoding back to
the network. Data output of the B3ZS/HDB3 decoder connects to the transmitter encoder
input. Line Code Violations (LCV) are not preserved in this loopback. The received data is still
presented to all receiver blocks and is present on the receiver outputs.
A dynamic change of this bit can cause loss of data for a few clock cycles until the channel is
internally synchronized. Activation or deactivation of a loopback causes internal circuits to
switch between clocks, after writing to this bit the microprocessor should not access any of the
device registers (read or write) for 20 slowest clock cycles.
Transmit FEAC Interrupt Enable—A control bit that allows interrupts from the FEAC
transmitter to be asserted on MINTR* pin when in DS3-C-Bit Parity mode. When in single
mode, the interrupt is asserted after every transmission of the code word written in the
Transmit FEAC Channel Byte register. When in repetitive mode, the interrupt is asserted once
the code word is transmitted 10 times.
FEAC Channel in Single Mode—In DS3-C-Bit Parity mode set to enable FEAC channel (in
the transmitter and the receiver) in a single mode, i.e., assert an interrupt after a single
reception or transmission of a code word. When clear, repetitive mode is enabled, i.e., an
interrupt is asserted after completion of 10 repetitions of code word reception or transmission.
In DS3-M13/M23, E3-G.751, and E3-G.832 modes, this bit has no effect.
Receive FEAC Stack Not Empty Interrupt Enable—A control bit that allows interrupts to
appear on MINTR* pin due to detection of the FEAC stack being not empty (i.e., Receive
FEAC stack byte is holding valid data). This bit is active both in single and repetitive modes.
Receive FEAC channel Idle Interrupt Enable—A control bit that allows interrupts to be
asserted on MINTR* pin due to detection of the start of an idle pattern over FEAC channel by
the receiver circuit. This bit is active both in single and repetitive modes.
Receive FEAC Interrupt Enable—A control bit that allows interrupts from the FEAC receiver
to appear on MINTR* pin when in DS3-C-Bit Parity mode. When a legal code word is
detected by the receiver (see Far-End Alarm and Control Channel Reception paragraph) this
interrupt is asserted.
RlineLp
6
Default after reset: 00
Direction: Read/Write
Modification: Bit 4: static, bits 0–2, 5–7: dynamic
Preliminary Information/Mindspeed Proprietary and Confidential
TxFEACIE
5
Mindspeed Technologies™
FEACSin
4
—
3
RxFEACSNEIE
2
RxFEACIdleIE
1
CX28365/6/4 Data Sheet
RxFEACIE
0
500028C