cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 161

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
Table 3-11. E3-G.832 Mode Field Interpretation
AutoRAI
ExtFEBE/Cj
500028C
DLMod[2]
0
0
0
0
1
1
1
1
DLMod[1]
Automatic RAI/RDI Generation Control—Set to enable automatic generation of the RAI or
RDI alarm in response to a fault detection. When set, an automatic assertion of the RAI bit in
E3-G.751 mode or RDI bit in E3-G.832 mode occurs once the receiver detects a LOS or OOF
condition. The automatic assertion continues as long as one or more of these conditions is
valid. The TxAlm [1] bit in the Mode Control register still effects RAI/RDI generation in E3
mode while this bit is set. When clear, RAI and RDI generation occurs due to the TxAlm [1]
bit in the Mode Control register and there is no automatic generation.
External FEBE/Justification Control—Set to enable insertion of FEBE or Justification Control
bits via the TEXTI pin. In DS3-C-Bit Parity mode, setting this bit enables insertion of FEBE
field via TEXTI pin. In DS3-M13/M23 mode, setting this bit enables insertion of all C-bits
(used for Justification Control) via TEXTI pin. In E3-G.751 mode, setting this bit enables
insertion of all Cj-bits (used for Justification Control) via TEXTI pin. In E3-G.832 mode,
setting this bit enables insertion of REI bit in MA byte via TEXTI pin. When this bit is cleared,
FEBE bits are transmitted automatically upon detection of framing or CP error by the receiver
according to the contents of FEBEC/PT field described in the Feature1 Control register,
0
0
1
1
0
0
1
1
DS3-C Bit Parity
DLMod [0] controls the reserved C-bits (C12, Cb2, Cb6, and Cb7) generation. When
set, these bits are inserted via the TEXTI pin. When cleared, these bits are
automatically generated as all 1s. In this mode, the bit is static.
NOTE:
DLMod[0]
Preliminary Information/Mindspeed Proprietary and Confidential
0
1
0
1
0
1
0
1
Mindspeed Technologies™
This bit has no effect in DS3 mode. Generation of an RAI alarm in DS3 mode is
controlled only by TxAlm bits.
Data link on the NR byte is disabled and the chip automatically generates an FF(h)
pattern on these bits. Data link on the GC byte is disabled and the chip
automatically generates an FF(h) pattern on these bits.
Data link on the NR byte is disabled, and the chip automatically generates an FF(h)
pattern on these bits. GC data is inserted via the TEXTI pin and is unaffected by the
internal HDLC circuit.
Data link on the NR byte is disabled and the chip automatically generates an FF(h)
pattern on these bits. GC data is inserted through the Transmit Data Link FIFO
buffer and is processed by the internal HDLC circuit.
NR data is inserted via the TEXTI pin, it is unaffected by the internal HDLC circuit.
Data link on GC byte is disabled and the chip automatically generates FF(h) pattern
on these bits.
NR data is inserted via the TEXTI pin; it is unaffected by the internal HDLC circuit.
GC data is inserted through the Transmit Data Link FIFO buffer and is processed
by the internal HDLC circuit.
NR data is inserted through the Transmit Data Link FIFO buffer and is processed
by the internal HDLC circuit. GC data is inserted via the TEXTI pin and is
unaffected by the internal HDLC circuit.
NR data is inserted through the Transmit Data Link FIFO buffer and is processed
by the internal HDLC circuit. Data link on GC byte is disabled and the chip
automatically generates an FF(h) pattern on these bits.
Both NR and GC data are inserted via the TEXTI pin; they are unaffected by the
internal HDLC circuit.
Description
Registers
3
-
51