cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 25

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
Table 1-2. Hardware Signal Definition, Transmit/Receive Line Interface (1 of 2)
500028C
TxCKO[0]
TxCKO[1]
TxCKO[2]
TxCKO[3]
TxCKO[4]
TxCKO[5]
TxCKO[6]
TxCKO[7]
TxCKO[8]
TxCKO[9]
TxCKO[10]
TxCKO[11]
TxPOSO/TxNRZ[0]
TxPOSO/TxNRZ[1]
TxPOSO/TxNRZ[2]
TxPOSO/TxNRZ[3]
TxPOSO/TxNRZ[4]
TxPOSO/TxNRZ[5]
TxPOSO/TxNRZ[6]
TxPOSO/TxNRZ[7]
TxPOSO/TxNRZ[8]
TxPOSO/TxNRZ[9]
TxPOSO/TxNRZ[10]
TxPOSO/TxNRZ[11]
TxNEGO[0]
TxNEGO[1]
TxNEGO[2]
TxNEGO[3]
TxNEGO[4]
TxNEGO[5]
TxNEGO[6]
TxNEGO[7]
TxNEGO[8]
TxNEGO[9]
TxNEGO[10]
TxNEGO[11]
RxCKI[0]
RxCKI[1]
RxCKI[2]
RxCKI[3]
RxCKI[4]
RxCKI[5]
RxCKI[6]
RxCKI[7]
RxCKI[8]
RxCKI[9]
RxCKI[10]
RxCKI[11]
Label
Pin
Framer Transmit Clock
Framer Transmit
Positive Rail or NRZ
Data
Framer Transmit
Negative Rail Data
Framer Receive Line
Clock
Signal
Name
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
CX28365
AD10
AD12
AC10
AB25
AB26
AC11
AD11
AD13
Pin#
AE11
AF10
W24
AD6
AD8
AD9
M24
U24
R24
N24
AE7
AE9
Y25
V25
Y26
V26
AA3
V24
P24
T25
AF4
AF6
AF8
T26
T24
W2
M1
W3
N2
R2
U2
R3
U3
P3
T3
V3
Y3
P1
T1
V1
CX28366
AC10
AC11
Pin#
AD6
AD8
AD9
AE7
AF4
AF6
AA3
—
—
—
—
—
—
W2
M1
W3
N2
R2
U2
R3
U3
P3
T3
V3
Y3
—
—
—
—
—
—
—
—
—
—
—
—
P1
T1
V1
—
—
—
—
—
—
CX28364
Pin#
AA3
W2
—
—
—
—
—
—
—
—
W3
M1
P3
V3
Y3
N2
R2
U2
P1
V1
R3
U3
T3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1
—
—
—
—
—
—
—
—
O/Z
O/Z
O/Z
I/O
I
Used to clock out the TxPOSO/
TxNRZ and TxNEGO framer
transmit outputs. Data is clocked
out on the rising or on the falling
edge of TxCKO according to
settings of bit LTxCkRis (Feature2
Control register).
These pins are transmitter positive
rail data (bipolar) or NRZ (unipolar
nonreturn-to-zero) data outputs.
The negative output (bipolar)
generated by the B3ZS/HDB3/AMI
encoder. Not used in unipolar NRZ
mode.
Used to clock in the RxPOSI and
RxNEGI or RxNRZ signals. In the
framer enable mode, the receiver
line clock operates at 44.736 MHz
(DS3 rate) or 34,368 MHz (E3
rate) Schmitt trigger input.
Note: RxCKI must be present for
proper register-read/writes.
Definition
Product Description
1
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