cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 87

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
Figure 2-16. Cell Delineation Process
Figure 2-17. Header Error Check Process
500028C
Errors Detected
(Drop Cell)
Detection
During the sync state of cell delineation, cells are passed to the UTOPIA interface if
the HEC is valid. If a single-bit error in the header is detected, the error is corrected
(optionally), and the cell is passed to the UTOPIA interface. If HEC checking is
enabled and HEC correcting is disabled (bit 3 in the CVAL register [0x0C]), cells with
single-bit HEC errors are discarded. If a multi-bit error is detected, the cell is dropped.
Once either type of error is noted, all subsequent errored cells are dropped until a
valid cell is received. This rule applies even for single-bit errors that could be
corrected. Once a valid cell is detected, the process begins again. (See
When LOCD occurs, an interrupt is generated and the cell processor automatically
enters the hunt mode. However, the cell is still being scrambled by the far-end
transmitter, leaving only the headers unscrambled. This means that the only repetitive
byte patterns in the data stream that meet the cell delineation criteria are valid headers.
Mode
Preliminary Information/Mindspeed Proprietary and Confidential
Hunt
Apparent Multi-bit Error (Drop Cell)
Mindspeed Technologies™
(Correct Error and Pass Cell)
1 Correct HEC
Apparent Single-bit Error
Cell Delineation in Sync State
No Errors Detected (Pass Cell)
7 Errored HECs
1 Errored HEC
Pre-Sync
Correction
Sync
Mode
6 Correct HECs
No Errors Detected
(Pass Cell)
Functional Description
Figure
500028_029
2-17).
500028_030
2
-
49