cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 138

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x28—ENCELLT (Transmit Cell Interrupt Control Register)
EnParErrInt
EnSOCErrInt
EnTxOvflInt
EnRxOvflInt
EnCellSentInt
EnBusCnflctInt
0x29—ENCELLR (Receive Cell Interrupt Control Register)
EnLOCDInt
EnHECDetInt
EnHECCorrInt
EnRcvrHldInt
EnCellRcvdInt
EnIdleRcvdInt
EnNonMatchInt
EnNonZerGFCInt
3-28
EnParErrInt
EnLOCDInt
7
7
EnHECDetInt
EnSOCErrInt
When written to a logical 1, this bit enables the Parity Error Interrupt.
When written to a logical 1, this bit enables the Start of Cell Error Interrupt.
When written to a logical 1, this bit enables the Transmit FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Receive FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Cell Sent Interrupt.
When written to a logical 1, this bit enables the Bus Conflict Interrupt.
When written to a logical 1, this bit enables a Loss of Cell Delineation Interrupt.
When written to a logical 1, this bit enables a HEC Error Detected Interrupt.
When written to a logical 1, this bit enables a HEC Error Corrected Interrupt.
When written to a logical 1, this bit enables a Receiver Hold Interrupt.
When written to a logical 1, this bit enables a Cell Received Interrupt.
When written to a logical 1, this bit enables an Idle Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-matching Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-zero GFC Received Interrupt.
6
6
The ENCELLT register controls which of the interrupts listed in the TxCellInt register
(0x2C) appear on CDInt (bit 2) of the PORTINTn Interrupt Control/Status register
(0xE90–0xE9B).
Default after reset: FC
The ENCELLR register controls which of the interrupts listed in the RxCellInt
register (0x2D) appear on CDInt (bit 2) of the PORTINTn Interrupt Control/Status
register (0xE90–0xE9B).
Default after reset: FF
Preliminary Information/Mindspeed Proprietary and Confidential
EnHECCorrInt
EnTxOvflInt
5
5
Mindspeed Technologies™
EnRcvrHldInt
EnRxOvflInt
4
4
EnCellRcvdInt EnIdleRcvdInt EnNonMatchIn
EnCellSentInt EnBusCnflctInt
3
3
2
2
—
1
1
t
CX28365/6/4 Data Sheet
EnNonZerGFCI
—
nt
0
0
500028C