cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 146

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
3.3
0x00—PLCPSEL (PLCP Mode Select Register)
PLCPSel
8kLock[1:0]
0x01—PLCPOVH (PLCP Overhead Control Register)
DisA1A2
DisPOI
DisB1
DisC1
AutoFEBE
InsFrmErr
InsBIPErr
InsFebeErr
3-36
PLCPSel
DisA1A2
7
7
(1)
(1)
(1)
8kLock[1]
When written to 1, PLCP mapping mode is selected; when written to 0, direct cell mapping
mode is selected.
00 = the transmit PLCP frame is locked to the receive PLCP frame reference
01 = the transmit PLCP frame is locked to the external 8 kHz reference input
10 = the transmit PLCP frame is generated with cycle stuffing for a nominal 8 kHz frame rate
11 = the transmit PLCP frame is locked to the external 8 kHz reference input
When written to 1, the A1 and A2 overhead octets in the PLCP frame are generated as 00h.
When written to 1, the POI octets in the PLCP frame are generated as 00h.
When written to 1, the B1 octet in the PLCP frame are generated as 00h.
When written to 1, the C1 octet in the PLCP frame are generated as 00h.
When written to 1, the FEBE field in the G1 octet are generated automatically in response to
received BIP errors; when written to 0, the FEBE field in the G1 octet are from the upper
nibble of the TXG1 register.
When written to 1, all A1 octets are inverted from the normal value for 1 PLCP frame.
When written to 1, the B1 octet are XORed with the value in the ERRPAT register for one
frame.
When written to 1, the upper nibble of the G1 octet are the value in the upper nibble of the
ERRPAT register for one frame.
DisPOI
PLCP Registers
6
6
The control/status register name assignments are the same for each port and are shown
below with the offset from the base address listed in the CX2836x address map.
Default after reset: 00
Default after reset: 08
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
8kLock[0]
DisB1
5
5
Mindspeed Technologies™
(1)
insertion has taken place. Clearing takes precedence over a simultaneous write
operation to this register.
These bits are cleared automatically by internal circuitry after the indicated error
DisC1
—
4
4
AutoFEBE
—
3
3
InsFrmErr(1)
—
2
2
InsBIPErr(1)
—
1
1
CX28365/6/4 Data Sheet
InsFebeErr(1)
—
0
0
500028C