cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 47

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cx28365

Manufacturer Part Number
cx28365
Description
X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
Manufacturer
Mindspeed Technologies
Datasheet
CX28365/6/4 Data Sheet
Table 2-1. Overhead Sourcing Methods
500028C
GENERAL NOTE:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
E3-G.751
E3-G.832
Mode
Either all fields enter via data stream, or only Justification Control bits (in DS3 M13/M23 and E3-G.751), or Stuff Opportunity
bits, or either justification control and stuff bits value or none.
In M12/M23 mode.
In C-bit Parity mode.
In non-SSM mode.
In SSM mode.
In either SSM or non-SSM mode.
Use only one overhead bit at a time to enable the LAPD datalink.
DS3
F-bits, M-bits (Frame)
X-bits (RAI)
P-bits (Parity)
7 Stuff Opportunity bits
C-bits (Justification Control)
Cb11 (AIC)
Cb13 (FEAC)
Cb3 (Path Parity)
Cb4 (FEBE)
Cb5 (DL)
Cb12, Cb2, Cb6–7
FAS (Frame)
A-bit (RAI)
N-bit (DL)
C
4 Stuff Opportunity bits
FA1, FA2 (Frame)
EM (BIP-8)
TR (Trail Trace)
MA RDI
MA REI
MA PT
MA PD
MA MI
MA TM/SSM
NR (DL)
GC (DL)
j-
bits (Justification Control)
(5)
(4)
(3)
(3)
(3)
Field
(3)
(6)
(3)
Preliminary Information/Mindspeed Proprietary and Confidential
(3)
(2)
(2)
Mindspeed Technologies™
Internal-Auto
Internal-Reg
(7)
(7)
Technique
External-Data
(1)
Functional Description
External-Pin
2
-
9

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