cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 65

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
Table 2-5. Setting the Error Insertion1 Control Register in E3-G.751 Mode
Table 2-6. Setting the Error Insertion1 Control Register in E3-G.832 Mode
500028C
Framing Error
(FA error)
BIP-8 parity
RDI
REI (FEBE)
Error
Error
FAS
RAI
FrmErrF
ParErr
YelErr
FEBEErr
FrmErrF
YelErr
Bit
Bit
E3-G.751 Mode
In the E3-G.751 mode of operation, setting bits at the Error Insertion1 Control register
can generate the errors listed in
E3-G.832 Mode
In the E3-G.832 mode of operation, setting bits at the Error Insertion1 Control register
can generate errors listed in
Line Coding Errors
In all basic modes of operation, line code errors can be forced when the transmitter
line side is operating in AMI or rail (HDB3/B3ZS encoding) mode.
In AMI or rail mode, a bipolar violation (BPV) can be inserted by setting the
LCVBPV bit in the Error Insertion2 Control register. The next 11 arriving after the bit
is set is changed to 1V (this restriction, rather than just reversing the next 1, prevents
inadvertently creating a zero-substitution sequence). Then, the encoding circuitry
adjusts itself to the reversed signal, causing the following output to be opposite from
the one that would have been produced had this error not been introduced; otherwise,
each error insertion would result in two consecutive BPVs.
example.
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
Set to
Set to
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Error insertion can be performed by the system only on Overhead bits that are set to
be automatically generated or taken from a register. Setting error insertion on
Overhead bits where the source is set to be from TEXTI pin, or inserted with payload,
produces undefined results.
1
1
1
1
1
1
Causes one bit of the next FAS sequence to be inverted.
Transmission of the opposite value of A-bit than expected or set. In this
case the next transmitted A-bit is cleared to 0 if an RAI should be
transmitted, and set to 1 if RAI is not expected (done by inverting the
next A-bit before transmission).
Transmission of one framing bit error. This causes one bit of the next FA
sequence to be inverted.
Transmission of a single incorrect bit in the next BIP-8 sequence by
inverting it before transmission.
Transmission of the value opposite of the RDI bit than expected or set.
The next transmitted RDI bit is cleared to 0 if an RDI should be
transmitted, and set to 1 if RDI is not expected (done by inverting the
next RDI bit before transmission).
Transmission of the value opposite from the expected one (by automatic
generation or its inserted value from external pin or with payload) at the
next MA REI bit position. This is done by inverting the next transmitted
MA REI bit.
Table
Table
2-6.
2-5.
Description
Description
Figure 2-11
Functional Description
illustrates an
2
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