cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 175

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
3.4.7
0x43—SR03 (Alarm Start Interrupt Status Register)
SEFStrt
LOSStrt
IdleStrt
YelStrt
AISStrt
OOFStrt
500028C
—
7
Severely Errored Frame Event Start—Set when the receiver detects an SEF condition. This bit
is cleared when this register is read. This bit is low in E3 modes since there is no defined SEF
alarm in these modes.
Loss of Signal Event Start—Set when the signal received is detected as lost by the receiver
prior to B3ZS/HDB3 decoding. This bit is cleared when this register is read.
Idle Event Start—Set when the receiver detects the start of an Idle event in DS3 mode. This bit
is cleared when this register is read. This is low in E3 modes, because there is no defined E3
idle signal.
Yellow Alarm Start—Set when the receiver detects the start of an RAI/RDI alarm. This bit is
cleared when this register is read.
AIS Alarm Start—Set when the receiver detects the start of an AIS alarm. This bit is cleared
when this register is read.
Out of Frame Event Start—Set when the channel gets into an OOF condition. This bit is
cleared when this register is read.
Dual-Edge Interrupt Status Registers
—
6
The Dual-Edge Interrupt Status registers provide indications for starting and ending
points of continuous events, to enable monitoring of the events length. All bits are set
due to an event and cleared when the register is read. In addition, every event bit (start
or end) is cleared upon setting the channel’s enable bit for that event to prevent an
immediate interrupt due to an old event.
Value after reset: 00
Direction: Read only
Value after enable: 00
Preliminary Information/Mindspeed Proprietary and Confidential
SEFStrt
5
Mindspeed Technologies™
LOSStrt
4
IdleStrt
3
YelStrt
2
AISStrt
1
OOFStrt
0
Registers
3
-
65