cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 195

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0xE11—INCH (INPORT Control Register [high byte])
InMode[11]
InMode[10]
InMode[9]
InMode[8]
0xE80–0xE8B—PORTn (Port N Mode Control Register)
FrmBypass
CDBypass
TxTimSel[1:0]
500028C
FrmBypass
—
7
7
CDBypass
When set to 0, the INPORT2[11] and INPORT1[11] pins function as input pins. When set to 1,
the INPORT2[11] and INPORT1[11] pins function as TxSync[11] and RxSync[11],
respectively.
When set to 0, the INPORT2[10] and INPORT1[10] pins function as input pins. When set to 1,
the INPORT2[10] and INPORT1[10] pins function as TxSync[10] and RxSync[10],
respectively.
When set to 0, the INPORT2[9] and INPORT1[9] pins function as input pins. When set to 1,
the INPORT2[9] and INPORT1[9] pins function as TxSync[9] and RxSync[9], respectively.
When set to 0, the INPORT2[8] and INPORT1[8] pins function as input pins. When set to 1,
the INPORT2[8] and INPORT1[8] pins function as TxSync[8] and RxSync[8], respectively.
When set to 1, the framer is bypassed—the data path goes directly between I/O pins and the
cell delineation block.
When set to 1, the cell delineation block is bypassed—the data path goes directly between I/O
pins and the framer block.
These bits control the clock source for the transmitter timing.
00 = REFCLK pin (global input)
01 = TxCKI pin (per port transmit clock)
10 = RxCKI pin (per port receive clock) (loop timing)
—
6
6
Value after reset: 00
Direction: Read/Write
Value after reset: 00
Direction: Read/Write
NOTE:
TxTimSel[1:0] TxTimSel[1:0] Out1Mode[1:0
Preliminary Information/Mindspeed Proprietary and Confidential
—
5
5
Mindspeed Technologies™
When selected, RxSync[i] is output as described in
an output or input, controlled by the bits TxSYOut (bit 3) and TxSYIn (bit 2) in CR05,
Feature 2 Control Register. Additional information on the use of the TxSync[i] signal
can be found in
—
4
4
Section
InMode[11]
2.1.1.
3
3
]
Out1Mode[1:0
InMode[10]
2
2
]
Section
InMode[9]
Out2Mode
2.1.2. TxSync[i] is either
1
1
InMode[8]
PortReset
0
0
Registers
3
-
85