cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 170

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
3.4.5
0x34—CR19 (Error Insertion1 Control Register)
FEBEErr
XDgrErr
YelErr
CPErr
ParDgrErr
3-60
FEBEErr
7
FEBE Error Insertion Control—Causes insertion of a FEBE error at the next opportunity.
In DS3 C-bit Parity mode, a FEBE error is the transmission of any combination of 1s and 0s
except 111. When a frame bit error or a C-bit parity is detected, transmission of the FEBE
error code, written in the FEBEC/PT field in Feature1 control register, takes place.
In E3-G.832 mode, REI (FEBE) bit is cleared to 0 when a BIP-8 error is detected in the EM
byte and set to 1 when the parity check in the EM byte is correct.
X-Bits Disagreement Error Insertion Control—Causes insertion of X-bits disagreement (i.e.,
the two X-bits in an M-frame are not equal) at the next opportunity. Valid in only DS3 mode.
Yellow Alarm Error Insertion Control—Causes insertion of RAI/RDI error at the next
opportunity. RAI error means transmission opposite of the expected value.
In DS3 mode, the two X-bits are set to 1 if an RAI should be transmitted and cleared to 0 if
RAI is not expected.
In E3-G.751 mode, The A-bit is cleared to 0 if an RAI should be transmitted and set to 1 if a
RAI is not expected.
In E3-G.832 mode, RDI bit clears to 0 if an RAI should be transmitted, and set to 1 if an RAI
is not expected.
C-Bit Parity Error Insertion Control—Causes insertion of a CP error at the next opportunity. A
CP error means transmission of an incorrect value in the three CP-bits. Valid only in DS3 C-
Bit Parity mode.
Parity Bits Disagreement Error Insertion Control—Causes insertion of P-bits disagreement
(i.e., the two P-bits in an M-frame are not equal) at the next opportunity. Valid only in DS3
mode.
XdgrErr
NOTE:
Error Insertion Control Registers
6
Error insertion registers, CR19 and CR20, enable single insertion of different errors.
Setting the relevant bit causes insertion of the requested error at the next valid
opportunity. The relevant control bit clears once the error is inserted. Therefore, the
control bits have to be polled before setting them for the next error insertion. Several
Error Insertion Control bits can be set at the same time; each one of them is cleared
when the appropriate error is inserted.
Default after reset: 00
Direction: Read/Write
Modification: Dynamic
Preliminary Information/Mindspeed Proprietary and Confidential
The software can only set the Error Insertion bits. Writing 0 to these bits leaves them
unaffected. Some of the bits are valid only in certain modes. When not valid, setting
the bits has no effect and they are not cleared. Reserved bits are cleared to 0. Value
after enabling Error Insertion Control bits = 0.
YelErr
5
Mindspeed Technologies™
CPErr
4
ParDgrErr
3
ParErr
2
FrmErrM
1
CX28365/6/4 Data Sheet
FrmErrF
0
500028C