cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 166

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
3.4.4
0x2D—CR13 (Transmit Data Link Control Register)
TxMsgIE
TxURIE
TxNEIE
TxFCSEn
0x2E—CR14 (Transmit Data Link Threshold Control Register)
TxNEThr[6:0]
3-56
—
—
7
7
TxNEThr[6]
Transmit Data Link Message Transmitted Interrupt Enable—Set to enable interrupt assertion
on MINTR* pin due to end of transmission of a full message.
Transmit Data Link FIFO Underrun Interrupt Enable—Set to enable interrupt assertion on
MINTR* pin due to Data Link FIFO underrun error.
Transmit Data Link FIFO Near-Empty Interrupt Enable—Set to enable interrupt assertion on
MINTR* pin due to the FIFO buffer being near empty.
Transmit Data Link FCS Calculation Enable—Set to enable FCS calculation over the
transmitted message and add it to the end of the transmitted message. When cleared, the FCS
calculation and addition are executed by the software.
Transmit Data Link FIFO Near Empty Threshold—Set to the threshold value, used to indicate
a Near-Empty FIFO event. The range of values available for this purpose is 0–126, where
00(h) is interpreted as 0, 01(h) is 1, etc. and 7E(h) is interpreted as 126.
Data Link Registers
—
6
6
The Transmit Data Link Control register (CR13) enables different modes and
interrupts in the Transmit Data Link operation.
Default after reset: 00
Direction: Read/Write
Modification: Bits 1–3: dynamic, bit 0–DL: static
Default after reset: 00
Direction: Read/Write
Modification: DL—static
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
TxNEThr[5]
—
5
5
Mindspeed Technologies™
Reserved bits, (—) in Control registers must be set to 0.
TxNEThr[4]
—
4
4
TxNEThr[3]
TxMsgIE
3
3
TxNEThr[2]
TxURIE
2
2
TxNEThr[1]
TxNEIE
1
1
CX28365/6/4 Data Sheet
TxNEThr[0]
TxFCSEn
0
0
500028C