cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 100

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.4.5
2.4.6
2-62
External Framer Interrupts and Chip Selects
Interrupts
The CX2836x can interface directly with a maximum of twelve external framers,
reducing the amount of external logic and address decode circuitry. Its twelve
interrupt inputs (MINTR*[0:11]) and twelve chip select outputs (LCS*[0:11]) provide
this function. Furthermore, the user can program the LCS* pins in IOMODE[CsPol]
to be either active high or active low to match the framer’s chip select input polarity.
When an external framer generates an interrupt, it asserts the associated LIntR* pin.
Each LIntR* pin is mapped to a corresponding ExInt bit in the appropriate Port’s
SUMINT register and the interrupt is forwarded, as described in
LCS* pin is asserted when an address within its range appears on the
microprocessor address bus and the MCS* pin is asserted. This output selects the
external framer being addressed. The framer’s address decoding logic further
determines which specific address is being accessed.
and their address ranges.
The CX2836x’s interrupt indications can be classified as either single- or dual-event;
a single-event interrupt is triggered by a status assertion; a dual-event interrupt is
triggered by either a status assertion or deassertion. Both types of interrupts are
further described in the following examples.
Single-event interrupt: When a parity error occurs on the UTOPIA transmit data bus,
an interrupt is generated on TXCELLINT[ParErrInt]. This bit is cleared when read.
Dual-event interrupt: When LOCD occurs, TXCELLINT[LOCD] is set to 1. This bit
is cleared when the register is read. Once cell delineation is recovered,
TXCELLINT[LOCD] is set to 1 again, generating another interrupt.
All interrupt bits have a corresponding enable bit. This allows software to disable or
mask interrupts as required.
NOTE:
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The interrupt bits in the Cell Delineator register group do not latch status unless the
respective interrupts are enabled. The affected registers are SUMINT (offset 0x00),
TXCELLINT (offset 0x2C), and RCXCELLINT (offset 0x2D).
Table 3-8
lists the LCS* pins
Section
CX28365/6/4 Data Sheet
2.4.6. An
500028C