cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 125

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cx28365

Manufacturer Part Number
cx28365
Description
X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
Manufacturer
Mindspeed Technologies
Datasheet
CX28365/6/4 Data Sheet
0x11—TXHDR2 (Transmit Cell Header Control Register 2)
TxHdr2[7:4]
TxHdr2[3:0]
0x12—TXHDR3 (Transmit Cell Header Control Register 3)
TxHdr3[7:0]
0x13—TXHDR4 (Transmit Cell Header Control Register 4)
TxHdr4[7:4]
TxHdr4[3:1]
TxHdr4[0]
500028C
TxHdr2[7]
TxHdr3[7]
TxHdr4[7]
7
7
7
TxHdr2[6]
TxHdr3[6]
TxHdr4[6]
VPI bits
VCI bits
VCI bits
VCI bits
Payload Type Indicator bits
Cell Loss Priority bit
6
6
6
The TXHDR2 register contains the second byte of the Transmit Cell Header. (See
0x10—TXHDR1.) These bits hold the Transmit Header values for Octet 2 of the
outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09).
Default after reset: 00
The TXHDR3 register contains the third byte of the Transmit Cell Header. (See
0x10—TXHDR1.) These bits hold the Transmit Header values for Octet 3 of the
outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09).
Default after reset: 00
The TXHDR4 register contains the fourth byte of the Transmit Cell Header (see
0x10—TXHDR1). These bits hold the Transmit Header values for Octet 4 of the
outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09).
Default after reset: 00
Preliminary Information/Mindspeed Proprietary and Confidential
TxHdr2[5]
TxHdr3[5]
TxHdr4[5]
5
5
5
Mindspeed Technologies™
TxHdr2[4]
TxHdr3[4]
TxHdr4[4]
4
4
4
TxHdr2[3]
TxHdr3[3]
TxHdr4[3]
3
3
3
TxHdr2[2]
TxHdr3[2]
TxHdr4[2]
2
2
2
TxHdr2[1]
TxHdr3[1]
TxHdr4[1]
1
1
1
TxHdr2[0]
TxHdr3[0]
TxHdr4[0]
0
0
0
Registers
3
-
15

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