cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 91

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.2.5
2.2.6
500028C
PLCP Transmit/Receive Synchronization
Cell Screening
PLCP frames must be transmitted at the same rate as they are received. For DS1 and
E1, long-term synchronization of the bit clock rates establish this. For DS3 and E3
rates, the payload data rate is independent of the line rate, and a separate timing/
synchronization mechanism is required.
The DS3 and E3 PLCPs both have a 125 s frame period. The reference clock for this
frame is taken from the received signal, or alternatively from an external reference
supplied to the 8 kHz clock input pin, 8KHZIn. In either case, the transmit circuit
generates one PLCP frame per reference frame.
All PLCP frame structures are based on a 125 s period; consequently, no stuffing is
required to synchronize the transmit and receive segments.
Clock and control inputs consist of the following:
A one-second clock output is provided to allow synchronization of status collection
for multiple CX2836x devices or for CX2836x devices and external line framers.
When a single CX2836x is used, OneSecOut should be connected to OneSecIn. This
timing output is derived from the external 8 kHz reference clock input on 8KHZIn.
The cell processor provides two optional types of cell screening. The first type, idle
cell rejection, prevents idle cells from being passed on. The second type, user traffic
screening, compares incoming bits to the values in the receive cell header registers.
Cells are rejected or accepted based on the bit patterns of their headers.
Idle cell rejection is enabled in bit 6 of the CVAL register (0x0C). If this bit is set to 1,
all incoming cells that match the contents of the Receive Idle Cell Header Control
registers, RXIDL1–4 (0x20–23), are rejected. Individual bits in the Receive Idle Cell
Mask Control registers, IDLMSK1–4 (0x24–27), can be set to 1 or Don’t Care,
causing the corresponding bits of the incoming cell to be treated as matching,
regardless of their value. If idle cell rejection is disabled, cells pass directly to user
traffic screening.
User traffic cell screening is similar to idle cell screening in that the incoming cells
are compared to the Receive Cell Header Control registers, RXHDR1–4 (0x18–1B).
Individual bits in the Receive Cell Mask Control registers, RXMSK1–4 (0x1C–1F),
can be set to 1 or Don’t Care, causing the corresponding bits of the incoming cell to be
treated as matching, regardless of their values.
The RejHdr bit (bit 7) in the CVAL register (0x0C) determines whether matching cells
are rejected or accepted; if it is set to 0, matching cells are accepted. If it is set to 1,
matching cells are rejected. See
Preliminary Information/Mindspeed Proprietary and Confidential
An external 8 kHz reference input for the PLCP at E3 and DS3
An external 8 kHz receiver output for the PLCP at E3 and DS3
A one-second input to synchronize status collection timing in multiple-port
applications
A reset input
Mindspeed Technologies™
Tables 2-10
and 2-11.
Functional Description
2
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