cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 128

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
3.2.3
0x0C—CVAL (Cell Validation Control Register)
RejHdr
DelIdle
EnRxCos
EnRxCellScr
EnHECCorr
DisHECChk
DisCellRcvr
DisLOCD
3-18
RejHdr
7
When written to a logical 1, this bit enables the Rejection of certain Header cells. When
enabled, cells with headers matching the RXHDRx/RXMSKx definition are rejected and all
others are accepted. When written to a logical 0, cells with matching headers are accepted and
cells with non-matching headers are rejected.
When written to a logical 1, this bit enables the Deletion of Idle Cells. When enabled, cells
matching the RXIDL/IDLMSK definition are deleted from the received cell stream. When
written to a logical 0, idle cells are included in the received stream.
When written to a logical 1, this bit enables the Receive HEC Coset. When written to a logical
0, the HEC Coset is disabled.
When written to a logical 1, this bit enables the Receive Cell Scrambler. When written to a
logical 0, the Receive Cell Scrambler is disabled.
When written to a logical 1, this bit enables HEC Correction. When written to a logical 0, HEC
Correction is disabled.
When written to a logical 1, this bit disables HEC Checking. When written to a logical 0, HEC
checking is performed as a cell validation criterion.
When written to a logical 1, this bit disables the Cell Receiver. When disabled, all cell
reception is disabled on the next cell boundary. When written to a logical 0, cell reception
begins or resumes on the next cell boundary.
When written to a logical 1, this bit disables Loss of Cell Delineation. When disabled, cells are
passed even if cell delineation has not been found. When written to a logical 0, cells are passed
only while cell alignment has been achieved.
DelIdle
Cell Receive Registers
6
This section describes the Traffic Reception control registers.
The CVAL register controls the validation of incoming cells.
Default after reset: 70
Preliminary Information/Mindspeed Proprietary and Confidential
EnRxCos
5
Mindspeed Technologies™
EnRxCellScr
4
EnHECCorr
3
DisHECChk
2
DisCellRcvr
1
CX28365/6/4 Data Sheet
DisLOCD
0
500028C