cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 176

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x44—SR04 (Alarm End Interrupt Status Register)
LOSEnd
IdleEnd
YelEnd
AISEnd
OOFEnd
3-66
—
7
Loss Of Signal Event End—Set when the received signal satisfies the criteria of correct signal
after being in a loss-of-signal state, prior to B3ZS/HDB3 decoding. This bit is cleared when
this register is read.
Idle Event End—Set when the receiver detects an end of an Idle event in DS3 mode. This bit is
cleared when this register is read. This bit is low in E3 modes, because there is no defined E3
idle signal.
Yellow Alarm End—Set when the receiver detects the end of an RAI/RDI alarm. This bit is
cleared when this register is read.
AIS Alarm End—Set when the receiver detects the end of an AIS alarm. This bit is cleared
when this register is read.
Out Of Frame Event End—Set when the channel goes into in-frame state again after being in
an OOF state. This bit is cleared when this register is read.
—
6
Value after reset: 00
Direction: Read only
Value after enable: 00
Preliminary Information/Mindspeed Proprietary and Confidential
—
5
Mindspeed Technologies™
LOSEnd
4
IdleEnd
3
YelEnd
2
AISEnd
1
CX28365/6/4 Data Sheet
OOFEnd
0
500028C