cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 130

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x1A—RXHDR3 (Receive Cell Header Control Register 3)
RxHdr3[7:0]
0x1B—RXHDR4 (Receive Cell Header Control Register 4)
RxHdr4[7:0]
0x1C—RXMSK1 (Receive Cell Mask Control Register 1)
RxMsk1[7:0]
3-20
RxMsk1[7]
RxHdr3[7]
RxHdr4[7]
7
7
7
RxMsk1[6]
RxHdr3[6]
RxHdr4[6]
These bits hold the Receive Header values for Octet 3 of the incoming cell.
These bits hold the Receive Header values for Octet 4 of the incoming cell.
These bits hold the Receive Header Mask for Octet 1 of the incoming cell.
6
6
6
The RXHDR3 register contains the third byte of the Receive Cell Header (see
0x18—RXHDR1).
Default after reset: 00
The RXHDR4 register contains the fourth byte of the Receive Cell Header (see
0x18—RXHDR1).
Default after reset: 00
The RXMSK1 register contains the first byte of the Receive Cell Mask. It modifies
ATM cell screening, which compares the Receive Cell Header Registers to the
incoming cells. Setting a bit in the Mask Register causes the corresponding bit in the
received ATM cell header to be disregarded for screening. For example, setting
RXMSK1 bit 0 to 1 causes ATM cells to be accepted with either 1 or 0 in the octet 1,
bit 0 position. Combinations of Receive Header Mask bits can select groups of ATM
VPI/VCIs for reception. This mask consists of 32 bits divided among four registers.
Default after reset: FF
Preliminary Information/Mindspeed Proprietary and Confidential
RxMsk1[5]
RxHdr3[5]
RxHdr4[5]
5
5
5
Mindspeed Technologies™
RxMsk1[4]
RxHdr3[4]
RxHdr4[4]
4
4
4
RxMsk1[3]
RxHdr3[3]
RxHdr4[3]
3
3
3
RxMsk1[2]
RxHdr3[2]
RxHdr4[2]
2
2
2
RxMsk1[1]
RxHdr3[1]
RxHdr4[1]
1
1
1
CX28365/6/4 Data Sheet
RxMsk1[0]
RxHdr3[0]
RxHdr4[0]
0
0
0
500028C