cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 201

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cx28365

Manufacturer Part Number
cx28365
Description
X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
Manufacturer
Mindspeed Technologies
Datasheet
CX28365/6/4 Data Sheet
4.4.1.1
Figure 4-4. Input Clock Timing
Table 4-4. Input Clock Timing
Figure 4-5. Line Side Receiver Input Data Setup/Hold Timing
500028C
GENERAL NOTE:
Symbol
1
1
2
3
4
5
Falling Edge
Rising Edge
There is a limit of 40%–60% duty cycle to all clocks.
Input Data
Input Data
TxCKI Frequency
RxCKI Frequency
Clock Width High/Low DS3
Clock Width High/Low E3
Clock Rise Time
Clock Fall Time
90%
50%
10%
Clock
Input Clock Timing
The following illustrates the various clocks applied to the CX28365 device and
associated parameters.
4
Preliminary Information/Mindspeed Proprietary and Confidential
Parameter
Mindspeed Technologies™
1
2
2
5
1
1
Minimum
11.6
8.8
34
34
2
3
Maximum
13.2
17.4
52
52
3
3
Specifications
Units
MHz
MHz
ns
ns
ns
ns
500028_043
500028_044
4
-
5

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