cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 152

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x22—CR02 (Alarm Start Interrupt Control Register)
SEFStrtIE
LOSStrtIE
IdleStrtIE
YelStrtIE
AISStrtIE
OOFStrtIE
3-42
—
7
Severely Errored Frame Start Interrupt Enable—Set to enable interrupts to be asserted on
MINTR* pin due to detection of SEF event start in DS3 mode. When the receiver detects an
SEF condition start, the interrupt is asserted and the SEFStrt bit in Alarm Start Interrupt Status
register is set. When this bit is cleared, detection of SEF start sets the appropriate status bit;
however, an interrupt is not activated. This bit has no effect in E3-G.751 and E3-G.832 modes.
Loss of Signal Start Interrupt Enable—Set to enable interrupts to be asserted on MINTR* pin,
due to a detection of LOS condition start in all modes. When a LOS condition start is detected,
the interrupt is asserted, and the LOSStrt bit in Alarm Start Interrupt Status register is set.
When this bit is cleared, detection of LOS start sets the appropriate status bit; however, an
interrupt is not activated.
Idle Interrupt Start Enable—Set to enable interrupts to appear on MINTR* due to detection of
Idle event start in DS3 mode. When the receiver detects an Idle start, the interrupt is asserted,
and the IdleStrt bit in Alarm Start Interrupt Status register is set. When this bit is cleared,
detection of Idle start sets the appropriate status bit; however, an interrupt is not activated. This
bit has no effect in E3-G.751 and E3-G.832 modes.
Yellow Alarm Start Interrupt Enable—Set to enable interrupts to be asserted on MINTR* due
to detection of RAI/RDI event start in all modes. When the receiver detects an RAI/RDI event
start, the interrupt is asserted, and YelStrt bit in Alarm Start Interrupt Status register is set.
When this bit is cleared, detection of RAI/RDI start sets the appropriate status bit; however, an
interrupt is not activated.
Alarm Indication Signal Start Interrupt Enable—Set to enable interrupts to be asserted on
MINTR* due to detection of AIS event start in all modes. When the receiver detects an AIS
event start, the interrupt is asserted, and AISStrt bit in Alarm Start Interrupt Status register is
set. When this bit is cleared, detection of AIS start sets the appropriate status bit; however, an
interrupt is not activated.
Out of Frame Start Interrupt Enable—Set to enable interrupts to be asserted on MINTR* pin
due to detection of OOF condition start in all modes. When the receiver detects an OOF
condition start, the interrupt is asserted, and OOFStrt bit in Alarm Start Interrupt Status
register is set. When this bit is cleared, detection of OOF start sets the appropriate status bit;
however, an interrupt is not activated.
—
6
Default after reset: 00
Direction: Read/Write
Modification: Dynamic
Preliminary Information/Mindspeed Proprietary and Confidential
SEFStrtIE
5
Mindspeed Technologies™
LOSStrtIE
4
IdleStrtIE
3
YelStrtIE
2
AISStrtIE
1
CX28365/6/4 Data Sheet
OOFStrtIE
0
500028C