cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 42

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
Figure 2-3. Tx System Side External Overhead Insertion (DS3 FEBE-only Example)
2-4
TEXTCKO(inv)
TEXTCKO
TxDATI
TxCKI
TEXTI
provides a clock pulse for the three C-bits in subframe 4 (FEBE bits). The FEBE bits
are inserted through the TEXTI pin and sampled by the next falling edge of TxCKI
clock after the pulse on TEXTCKO. This indicates, to the system, that the framer
expects a new FEBE bit. The data on TEXTI must satisfy setup and hold times around
the falling edge of TxCKI clock when it is sampled. TxDATI serial data input is also
shown. TEXTI and TxDATI have the same timing.
There are three modes for the pin TxSync[i]. The modes are controlled by the
Feature2 control register (CR05i) bits TXSYOut (b3) and TXSYIn (b2).
1. Reset (TXSYOut = 0 and TXSYIn = 0)
When the chip is in a reset condition, TxSync[i] is in a high Z state.
2. Input (TXSYOut = 0 and TXSYIn = 1)
At reset, the framer is not synchronized and does not provide internal synchronization.
TEXTCK and TXGAPCK are disabled (long gap) until TxSync[i] is asserted. At least
one TxSync[i] signal is expected to start the internal framer synchronization. It is
sampled with the falling edge of the input clock TxCKI.
When asserted synchronously with the internal framer timing, no resynchronization
occurs. There is a transition from low to high between the last sampling edge of frame
N and the first sampling edge of frame N+1.
When asserted asynchronously with the internal framer timing, resynchronization
occurs within one frame time.
In all cases, the first bit of the new frame is asserted on TXDATI at the same time and
is available on the first or next sampling edge of TXCKI. The framer maintains
synchronization from the last asserted TxSync[i] signal.
3) Output (TXSYOut = 1 and TXSYIn = 0)
There are two modes for the TxSync[i] pin when used for an output signal. The modes
are controlled by the Feature2 control register (CR05i) TxOvhMrk bit (b4). In the
output modes, it is sampled with the rising edge of the input clock TxCKI.
Preliminary Information/Mindspeed Proprietary and Confidential
Cb41
Setup+Hold
169 bits
Cb41
84 Data + F2 bit
Mindspeed Technologies™
+84 Data
Subframe 4 of Frame I
Cb42
Setup+Hold
169 bits
Cb42
84 Data + F3 bit
+84 Data
Cb43
Setup+Hold
4419 bits
Rest of Frame I +
Cb43
Part Frame I+1
Subframe 4 of Frame I+1
Setup+Hold
CX28365/6/4 Data Sheet
Cb41
Cb41
500028C
500028_017